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Keywords: IP Logic Design Engineer, Location: Santa Clara, CA

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IP Logic Design Engineer

, we are building a better tomorrow. Who We Are This position is an IP Logic Design Engineer role in the Edge Acceleration IP group... You Are Your responsibilities are as follows but not limited to: You will be part of IP design team working on Audio subsystem Soft IP for client...

Company: Intel
Location: Santa Clara, CA
Posted Date: 06 Apr 2025

Senior IP Logic Design Engineer

level (RTL) development for the IP block and implements the specification for logic components Ensures quality of design... Applies various strategies, tools and methods to write RTL and optimize logic to qualify the design to meet power, performance...

Company: Intel
Location: Santa Clara, CA
Posted Date: 19 Feb 2025

Logic Design Methodology Engineer

Job Details: Job Description: Come join us as a Logic Design Methodology Engineer and together let's grow... and develop the next leading technology. As the Logic Design Methodology Engineer of the Platform Engineering Solution Group...

Company: Intel
Location: Santa Clara, CA
Posted Date: 28 Mar 2025

Senior Logic Design Engineer

. If this is your passion, come join us to do something wonderful. As a Senior Logic Design Engineer your responsibilities will include... logic of IP blocks and subsystems into a full chip SoC or discrete component design. Participates in the definition...

Company: Intel
Location: Santa Clara, CA
Posted Date: 26 Mar 2025

CXLCM micro-Architect/Senior Logic Design Engineer

, come join us to do something wonderful. The IP Engineering Group is looking for energetic and passionate senior Design leaders to work closely... with established ASIC design team for advanced digital IO controller (like PCIe, UPI, CXL, IOMMU etc.) IP implementation on cutting...

Company: Intel
Location: Santa Clara, CA
Posted Date: 20 Mar 2025

Senior IP Design Verification Engineer

. Determines architecture design, logic design, and system simulation. Defines module interfaces/formats for simulation. Performs... Logic design for integration of cell libraries, functional units and subsystems into SoC full chip designs, Register...

Company: Intel
Location: Santa Clara, CA
Posted Date: 18 Feb 2025

GPU Design Verification Engineer

for you. We are looking for Graphics Design/Verification Engineer to join our team. In this position, you will be playing a key role in the pre-silicon... in silicon design development 1+ year experience in the following: Test Bench bring-up at IP level and strong programming...

Company: Intel
Location: Santa Clara, CA
Posted Date: 07 Apr 2025

GPU Design Verification Engineer

for you. We are looking for Graphics Design/Verification Engineer to join our team. In this position, you will be playing a key role in the pre-silicon... of experience in silicon design development 3 years experience in the following: Test Bench bring-up at IP level...

Company: Intel
Location: Santa Clara, CA
Posted Date: 31 Mar 2025

Physical Design Engineer

and route of RTL blocks for high speed datapath and control logic applications, automated design flows for clock tree synthesis.../area, and design cycle time reduction. You will also support floorplanning, establishing design methodology, IP integration...

Posted Date: 29 Mar 2025

Design Verification Engineer

Job Details: Job Description: Come join us as a Design Verification Engineer and together let's grow and develop.... Key Responsibilities: Performs functional logic verification of an integrated SubSystem to ensure design will meet...

Company: Intel
Location: Santa Clara, CA
Posted Date: 21 Mar 2025

Senior Staff Hardware Design Engineer

and expertise in electrical circuit design for power supply, clock distribution, control logic functions, and in basic communication..., above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As a Hardware Design Senior Staff...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 22 Feb 2025
Salary: $143200 - 214500 per year

Design Verification, Senior Staff Engineer

Expect ASIC design engineer responsible for the design, verification and evaluation of digital circuits in high-speed data... with Analog/DSP/Digital Design/FW/AE teams to deliver the competitive SerDes IP solutions for all the Marvell product lines...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 29 Jan 2025
Salary: $121840 - 182500 per year

ASIC/RTL Design Engineer - Senior (US)

, SATA and Client internal IP's. Successful candidates will be responsible for leading, and participating in, the design...; - Knowledge AND hand-on experience from industry ASIC design flow including RTL coding, IP Integration, debugging/verification...

Company: Managed Staffing
Location: Santa Clara, CA
Posted Date: 14 Feb 2025

ASIC/RTL Design Engineer - Senior (US)

, SATA and Client internal IP's. Successful candidates will be responsible for leading, and participating in, the design...; - Knowledge AND hand-on experience from industry ASIC design flow including RTL coding, IP Integration, debugging/verification...

Company: Managed Staffing
Location: Santa Clara, CA
Posted Date: 13 Feb 2025

Sr Principal Design Engineer

technology. We develop the architecture, IP development, SOC , create the physical design, and work with the world’s leading data... or Own a significant section of our Switch design IPs Work closely with Architects and define IP micro-architecture and SOC...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 08 Feb 2025

Senior Software Engineer - Cloud Automation

Company Description It all started in sunny San Diego, California in 2004 when a visionary engineer, Fred Luddy, saw... better for everyone. Job Description ServiceNow is seeking a Senior Software Engineer, to join our team building highly scalable Cloud Automation software. The team...

Company: ServiceNow
Location: Santa Clara, CA
Posted Date: 13 Mar 2025

SoC Emulation Firmware Engineer

to: Conducting functional logic verification of an integrated SoC to ensure design meets specifications. Developing and refining... Emulation Firmware Engineer, you will play a critical role in developing cutting-edge firmware for System-on-Chip (SoC...

Company: Intel
Location: Santa Clara, CA
Posted Date: 28 Feb 2025

Graphics FE Integration Engineer

parameters, physical constraints, DFT logic and power intent. Description As a GPU Design Integration Engineer..., you will be responsible for: - RTL integration, partitioning, design analysis, qualification, packaging and delivery. - Run logic equivalence...

Company: Apple
Location: Santa Clara, CA
Posted Date: 16 Jan 2025

Graphics FE Integration Engineer

parameters, physical constraints, DFT logic and power intent. Description As a GPU Design Integration Engineer... with the one of the following scripting languages: Perl/Ruby/Python. Preferred Qualifications Proficiency in logic design...

Company: Apple
Location: Santa Clara, CA
Posted Date: 16 Jan 2025

EDA Hardware Engineer

of experience. Your experience in following area: Logic and memory design principles, VLSI design flow and VLSI CAD algorithms... experiences and or schoolwork/classes/research. Preferred Qualifications: Detailed understanding of logic and array design...

Company: Intel
Location: Santa Clara, CA
Posted Date: 15 Mar 2025