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Keywords: Senior IP Design Verification Engineer, Location: Santa Clara, CA

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Senior IP Design Verification Engineer

but not limited to: Oversees definition, design, verification, and documentation for SoC (System on a Chip) development... developing bus functional models for unit level verification or Verification IP development Preferred skills and experience...

Company: Intel
Location: Santa Clara, CA
Posted Date: 18 Feb 2025

Design Verification, Senior Staff Engineer

Expect ASIC design engineer responsible for the design, verification and evaluation of digital circuits in high-speed data... development and execution. As a senior member in the team, he/she will focus on improving the design verification methodology...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 29 Jan 2025
Salary: $121840 - 182500 per year

Senior IP Logic Design Engineer

level (RTL) development for the IP block and implements the specification for logic components Ensures quality of design... through clean design partitioning, clear microarchitectural documentation, reviewing RTL design and verification of features...

Company: Intel
Location: Santa Clara, CA
Posted Date: 19 Feb 2025

Senior Principal Engineer, Verification (Ethernet, Serdes, UVM)

a highly skilled and experienced Senior Principal Verification Engineer to join our dynamic team in Santa Clara, CA. The ideal.... As a Senior Principal Verification Engineer, you will play a critical role in ensuring the quality and reliability of our cutting...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 28 Feb 2025

Senior E/E & Semiconductor Engineer - Digital Design (RTL) Engineer

, configuration registers, etc. Knowledge of JESD204C block design and related design/verification experience (includes licensed IP...Job Role: RTL Engineer Job Location: Santa Clara CA Job description: We are seeking Digital Design (RTL) engineer...

Company: Capgemini
Location: Santa Clara, CA
Posted Date: 29 Jan 2025

ASIC/RTL Design Engineer - Senior (US)

; - Knowledge AND hand-on experience from industry ASIC design flow including RTL coding, IP Integration, debugging/verification..., SATA and Client internal IP's. Successful candidates will be responsible for leading, and participating in, the design...

Company: Managed Staffing
Location: Santa Clara, CA
Posted Date: 14 Feb 2025

ASIC/RTL Design Engineer - Senior (US)

; - Knowledge AND hand-on experience from industry ASIC design flow including RTL coding, IP Integration, debugging/verification..., SATA and Client internal IP's. Successful candidates will be responsible for leading, and participating in, the design...

Company: Managed Staffing
Location: Santa Clara, CA
Posted Date: 13 Feb 2025

Digital Design Engineer, Senior Staff

. We develop the architecture, collaborate on IP development, create the physical design, and work with the world’s leading AI data... techniques and best practices Work with the physical design teams for synthesis and timing signoff. Work with the Verification...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 16 Jan 2025
Salary: $124160 - 186000 per year

PMTS Silicon Design Engineer

_ PMTS SILICON DESIGN ENGINEER THE ROLE: We are seeking a seasoned SoC Architect with expertise or significant interest.... You are meticulous about Power, Performance and Area while driving schedule and managing cost. This senior role will stretch...

Posted Date: 15 Feb 2025

Sr Sales Executive Semiconductor Chip Design Engineering Services

of semiconductor ecosystem, including relationships with foundries, EDA companies, and IP providers. · Background in ASIC Design...Job Description Title : Sr Sales Executive Semiconductor Services Chip Design Location: SFO, Bay Area, California...

Posted Date: 19 Feb 2025