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Keywords: RTL Automation Design Engineer, Location: San Jose, CA

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RTL Automation Design Engineer

_ THE ROLE: AMD is seeking a ASIC Design Engineer with specific experience with scripting skills around the EDA tool... system which the candidate will assist in improving to meet the needs of the RTL design teams. THE PERSON: High energy...

Posted Date: 12 Apr 2025

Silicon Design Verification Engineer

_ SILICON DESIGN VERIFICATION ENGINEER THE ROLE: We are looking for an adaptive, self-motivative design verification... engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMD...

Posted Date: 28 Mar 2025

ASIC Design Engineer, Senior Technical Leader

You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding of timing constraints, including clock... timing in multiple timing modes. Option to also do block level RTL design or block or top-level IP integration. Helping...

Company: Cisco Systems
Location: San Jose, CA
Posted Date: 20 Feb 2025

Physical Design Engineer (Place & Route)

to join us in shaping the future. What you will be responsible for: Physical Design: You will handle all aspects of physical design... and implementation from RTL to GDS in an advanced node process (sub 12nm) Custom Flow: You better be comfortable setting up your own APR...

Posted Date: 26 Feb 2025

Silicon Design Verification Engineer

: You have a passion for digital design, and verification in general. You are a team player who has excellent communication skills... Define test plans, test benches, and tests using System Verilog and UVM Debug RTL and Gate simulations and work with HW...

Posted Date: 20 Jan 2025

ASIC Design Technical Leader - Design & Timing Constraints Focus

You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding of timing constraints, including clock... timing in multiple timing modes. Option to also do block level RTL design or block or top-level IP integration. Helping...

Company: Cisco Systems
Location: San Jose, CA
Posted Date: 01 Apr 2025

Static Timing Analysis Engineer

) and Fusion compiler/design compiler(Synopsis). Good to have: Automation. Good scripting skills with Perl and TCL. Prior...Job Role: We are looking for a Static Timing Analysis Engineer with atleast 8 years of experience in Functional...

Company: Nesco Resource
Location: San Jose, CA
Posted Date: 10 Apr 2025

ASIC Engineering Technical Leader - SDC

You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding of timing constraints, including clock... as early as possible in design cycle. Review block level SDCs and clocking diagrams and mentor other RTL design owners on SDC...

Company: Cisco Systems
Location: San Jose, CA
Posted Date: 02 Apr 2025