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Keywords: Physical Design Engineer (Place & Route), Location: San Jose, CA

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Physical Design Engineer (Place & Route)

to join us in shaping the future. What you will be responsible for: Physical Design: You will handle all aspects of physical design... around these limitations Design Optimization: You will identify physical bottlenecks in the design, going as far down as standard...

Posted Date: 26 Feb 2025

Principal Application Engineer - Physical Design

including Synthesis, Place and Route, Design Closure, and timing/power signoff Guide customers on how to best utilize Cadence... and Route, IR Drop, backend design timing and power closure Experience with advanced nodes 10nm and below Experience...

Posted Date: 04 Jan 2025
Salary: $120400 - 223600 per year

R&D Engineer Physical Design

with Physical verification and place-and-route tools for ASIC/SoC design is essential Education/Experience: BS degree..., floor planning, place and route, clock tree synthesis, and physical verification. This role involves contributing...

Company: Broadcom
Location: San Jose, CA
Posted Date: 01 Mar 2025
Salary: $119000 - 190000 per year

R&D Engineer Physical Design

synthesis, design for test, floorplanning, place and route, clock methodology, power planning and analysis, timing closure..., signal integrity and physical design checks. Participate in large complex design implementations using the latest technology...

Company: Broadcom
Location: San Jose, CA
Posted Date: 19 Jan 2025
Salary: $119000 - 190000 per year

R&D Engineer Physical Design

Broadcom is looking for a Design Implementation Engineer with demonstrated expertise across key areas such as synthesis... timing constraints to ensure accurate and efficient timing analysis and closure. Expertise in place-and-route tools for ASIC...

Company: Broadcom
Location: San Jose, CA
Posted Date: 01 Mar 2025
Salary: $119000 - 190000 per year

Backend Digital Design Sr Principal Application Engineer

including Place and Route, Design Closure, and timing/power signoff Guide customers on how to best utilize Cadence technologies... flows and backend EDA tools including Place and Route, IR Drop, backend design timing and power closure Experience...

Posted Date: 12 Feb 2025

Principal FPGA Design Engineer

using Verilog Experience with high end Xilinx(AMD) FPGAs including using Vivado tool for simulation, Place and route... is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies...

Posted Date: 10 Jan 2025
Salary: $131600 - 244400 per year

Principal FPGA Design Engineer

using Verilog Experience with high end Xilinx(AMD) FPGAs including using Vivado tool for simulation, Place and route... is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies...

Posted Date: 10 Jan 2025
Salary: $131600 - 244400 per year

Senior ASIC Design Engineer

and close code coverage. Work closely with the physical design team to close design timing and place-and-route issues.... Help define, evolve, and support our design methodology. Collaborate with the verification team to address design bugs...

Company: Cisco Systems
Location: San Jose, CA
Posted Date: 31 Jan 2025

ASIC Design Engineer

code coverage. Work closely with physical design team to close design timing and place-and-route issues. Triage, debug.... What You'll Do You will author design specifications and participate in micro-architecture specification reviews. Implement...

Company: Cisco Systems
Location: San Jose, CA
Posted Date: 29 Jan 2025
Salary: $133300 - 186800 per year

ASIC Design Engineer, Senior Technical Leader

to close design timing and place-and-route issues. Perform diagnostic and post silicon validation tests in the lab. Work.... Collaborate with the verification team to address design bugs and close code coverage. Work closely with physical design team...

Company: Cisco Systems
Location: San Jose, CA
Posted Date: 16 Jan 2025

ASIC Design Engineer, Technical Leader

to close design timing and place-and-route issues. Triage, debug, and root cause simulation, software bring-up, and customer.... Collaborate with the verification team to address design bugs and close code coverage. Work closely with physical design team...

Company: Cisco Systems
Location: San Jose, CA
Posted Date: 16 Jan 2025

Principal Software Engineer - C++

applications, including synthesis, place and route, timing analysis, and optimizations. Proficiency in C++ programming...This is an exciting new opportunity for a Principal C++ Software Engineer at Cadence: Cadence has been a driving force...

Posted Date: 27 Feb 2025

Principal C++ Software Engineer - Protium Prototyping Platform

like synthesis/place and route/timing/optimizations Excellent programming skills in C/C++, Object Oriented Programming, Multi... is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies...

Posted Date: 10 Jan 2025
Salary: $131600 - 244400 per year

Principal C++ Software Engineer - Protium Prototyping Platform

of EDA applications like synthesis/place and route/timing/optimizations Excellent programming skills in C/C++, Object... is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies...

Posted Date: 10 Jan 2025
Salary: $131600 - 244400 per year

Principal Software Engineer - Protium Prototyping Platform

like synthesis/place/route/timing/optimizations Excellent programming skills in C/C++, Object Oriented Programming, Multi-threaded... is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies...

Posted Date: 10 Jan 2025
Salary: $131600 - 244400 per year

Senior Synthesis Engineer

Engineer, you will be responsible for preparing SDC and running physical synthesis using the Synopsys Fusion Compiler for TSMC... above 1.2GHz. You will collaborate with the Physical Design team to meet timing across multiple corners and execute ECOs in the PT-SI flow for timing...

Posted Date: 22 Feb 2025

Senior Signal & Power Integrity Engineer

is seeking a Senior Signal & Power Integrity Engineer for the analysis and design of high-speed components, interfaces, and power... physical measurements to collect data for design validation and simulation correlations Driving methodology enhancements...

Company: Cisco Systems
Location: San Jose, CA
Posted Date: 21 Feb 2025

ASIC IMPLEMENTATION ENGINEER

, floorplanning, place and route, clock methodology, power planning and analysis, timing closure, signal integrity and physical design...ASIC implementation engineer with demonstrated expertise in multiple disciplines including synthesis, design for test...

Company: Broadcom
Location: San Jose, CA
Posted Date: 19 Jan 2025
Salary: $119000 - 190000 per year

ASIC IMPLEMENTATION ENGINEER

, floorplanning, place and route, clock methodology, power planning and analysis, timing closure, signal integrity and physical design...ASIC implementation engineer with demonstrated expertise in multiple disciplines including synthesis, design for test...

Company: Broadcom
Location: San Jose, CA
Posted Date: 18 Jan 2025
Salary: $119000 - 190000 per year