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Keywords: Physical Design Engineer (Place & Route), Location: San Jose, CA

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Physical Design Engineer (Place & Route)

to join us in shaping the future. What you will be responsible for: Physical Design: You will handle all aspects of physical design... around these limitations Design Optimization: You will identify physical bottlenecks in the design, going as far down as standard...

Posted Date: 26 Feb 2025

R&D Engineer Physical Design

with Physical verification and place-and-route tools for ASIC/SoC design is essential Education/Experience: BS degree..., floor planning, place and route, clock tree synthesis, and physical verification. This role involves contributing...

Company: Broadcom
Location: San Jose, CA
Posted Date: 01 Mar 2025
Salary: $119000 - 190000 per year

R&D Engineer Physical Design

synthesis, design for test, floorplanning, place and route, clock methodology, power planning and analysis, timing closure..., signal integrity and physical design checks. Participate in large complex design implementations using the latest technology...

Company: Broadcom
Location: San Jose, CA
Posted Date: 18 Jan 2025
Salary: $119000 - 190000 per year

R&D Engineer Physical Design

Broadcom is looking for a Design Implementation Engineer with demonstrated expertise across key areas such as synthesis... timing constraints to ensure accurate and efficient timing analysis and closure. Expertise in place-and-route tools for ASIC...

Company: Broadcom
Location: San Jose, CA
Posted Date: 01 Mar 2025
Salary: $119000 - 190000 per year

Backend Digital Design Sr Principal Application Engineer

including Place and Route, Design Closure, and timing/power signoff Guide customers on how to best utilize Cadence technologies... flows and backend EDA tools including Place and Route, IR Drop, backend design timing and power closure Experience...

Posted Date: 12 Feb 2025

ASIC Design Engineer

and close code coverage. Work closely with physical design team to close design timing and place-and-route issues. Triage.... You will work with exceptional talent with vast ASIC design and development expertise. With Cisco being a systems company...

Company: Cisco Systems
Location: San Jose, CA
Posted Date: 18 Mar 2025
Salary: $133300 - 186800 per year

Senior ASIC Design Engineer

design bugs and close code coverage. Work closely with the physical design team to close design timing and place-and-route... functional coverage. Help define, evolve, and support our design methodology. Collaborate with the verification team to address...

Company: Cisco Systems
Location: San Jose, CA
Posted Date: 07 Mar 2025

Senior ASIC Design Engineer

and close code coverage. Work closely with the physical design team to close design timing and place-and-route issues.... Help define, evolve, and support our design methodology. Collaborate with the verification team to address design bugs...

Company: Cisco Systems
Location: San Jose, CA
Posted Date: 31 Jan 2025

Sr. Principal STA/PD Solutions Engineer

, EMIR and/or physical design and ensure integrity of delivered solutions. Individual should be able to efficiently work... with Cadence R&D to enable various tool feature and close tool bug fixes. Work on various aspects of physical design including...

Posted Date: 13 Mar 2025

Signal Integrity Engineer

Modeling and analyzing power delivery networks Performing physical measurements to collect data for design validation... you to be part of our team. What You'll Do: As a Signal Integrity (SI) Engineer, you will be a part of an engineering team...

Company: Cisco Systems
Location: San Jose, CA
Posted Date: 17 Apr 2025

Sr. Staff IC CAD Engineer

such as Cadence schematic entry, mixed mode circuit simulation, layout design, layout verification, logic synthesis, place & route... density. We are seeking a highly motivated Sr. Staff CAD Engineer to join our dynamic engineering team in capitalizing...

Location: San Jose, CA
Posted Date: 17 Apr 2025

Senior Staff Emulation Engineer - ZEBU

, Emulation, FPGA based validation, DFT, RTL2GDSII, Physical Design using ICC2 and Innovus, Mask Layout, Firmware, Silicon Bringup... for emulation products. The engineer will also design and develop tests in VHDL/Verilog/System Verilog languages, resolving...

Company: Prodapt
Location: San Jose, CA
Posted Date: 10 Mar 2025

Senior Staff Emulation Engineer - ZEBU

based verification, Emulation, FPGA based validation, DFT, RTL2GDSII, Physical Design using ICC2 and Innovus, Mask Layout...) and various solutions for emulation products. The engineer will also design and develop tests in VHDL/Verilog/System Verilog...

Company: Prodapt
Location: San Jose, CA
Posted Date: 08 Mar 2025