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Keywords: Design verification engineer, Location: Austin, TX

Page: 1

Sr. Principal Design verification engineer

/ Processor based SOC architecture and digital design fundamentals Skilled in many aspects of digital verification... verification / IP Verification Knowledge of Verilog/System Verilog, digital simulation and debug Knowledge of HS/LS Protocols...

Location: Austin, TX
Posted Date: 05 Feb 2025

Design verification engineer

ASIC Engineer, Design Verification Responsibilities Define and implement IP/SoC verification plans, build verification.... Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage...

Company: Cloudious
Location: Austin, TX
Posted Date: 05 Apr 2025

Senior SoC Design Verification Engineer (remote)

Senior SoC Design Verification Engineer Remote / work from home US Citizen or US Permanent Resident Full-time... verification of complex SoCs using UVM and SystemVerilog. As SoC Design Verification Engineer, you will collaborate with a small...

Location: Austin, TX
Posted Date: 05 Apr 2025

Design Verification Engineer

_ THE ROLE: As a design verification engineer, you will work with formal experts and designers to verify formal properties... components in SystemVerilog and UVM along with formal to achieve verification of the design Responsible for verification quality...

Location: Austin, TX
Posted Date: 02 Apr 2025

ASIC Engineer, Design Verification

Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals... silicon success. ASIC Engineer, Design Verification Responsibilities Define and implement IP/SoC verification plans, build...

Company: Meta
Posted Date: 19 Mar 2025

Staff Engineer, Design Verification Engineering

Communications & Cloud team is seeking a motivated design engineer to provide support to our Cloud Power BU located at ADI’s San Jose... provides unique learning opportunities related to advanced mixed signal design verification techniques. Responsibilities...

Company: Analog Devices
Location: Austin, TX
Posted Date: 16 Mar 2025
Salary: $118988 - 178481 per year

Front-End Infrastructure / CAD Engineer (FE Design Verification)

is seeking a highly skilled and motivated Engineer with extensive experience in Front-End (FE) Design Verification flows, tools...-leading EDA vendors. Development & Maintenance of Verification Flows: You design, support, and continuously improve highly...

Company: 삼성전자
Location: Austin, TX
Posted Date: 12 Mar 2025

ASIC Engineer, Design Verification

Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals... towards creating a first-pass silicon success. ASIC Engineer, Design Verification Responsibilities Define and implement block/IP...

Company: Meta
Posted Date: 09 Mar 2025

ASIC Engineer, Memory Management Design Verification

Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals... teams towards creating a first-pass silicon success. ASIC Engineer, Memory Management Design Verification Responsibilities...

Company: Meta
Posted Date: 27 Feb 2025

Custom Circuits Design Verification Engineer

SoCs that make their way into Apple products. We are looking for a Design Verification Engineer who will enable bug-free.... Design Verification Engineers at Apple are responsible for verifying the functionality and performance of Appleʼs premier...

Company: Apple
Location: Austin, TX
Posted Date: 02 Feb 2025

Cellular SOC Design Verification Engineer

Verification Engineer on our team, you'll be at the center of the verification effort within our silicon design group responsible... scale SOC design, Complex verification test benches, different types of SOC architectures, multiple high speed protocols...

Company: Apple
Location: Austin, TX
Posted Date: 10 Jan 2025

Sr. Design Verification Engineer (Coherent Interconnect)

of people around the world. Come build with us! Role and Responsibilities As a Sr. Design Verification Engineer.... This is an individual contributor role involved in hands-on project execution. A strong background in Design Verification, TB architect...

Company: 삼성전자
Location: Austin, TX
Posted Date: 09 Jan 2025

Principal Design Verification Engineer (Coherent Interconnect)

of people around the world. Come build with us! Role and Responsibilities As a Principal Design Verification Engineer... with Physical design teams, running and debugging gate-level simulations You work with Performance verification teams to help...

Company: 삼성전자
Location: Austin, TX
Posted Date: 09 Jan 2025

Design Verification Engineer

in communication systems - Familiarity with Matlab - Modem design verification experience - System C or Matlab model : development... a state of the art verification environment to facilitate testing of the RTL against reference Matlab/C models · Develop...

Company: Amazon
Location: Austin, TX
Posted Date: 05 Apr 2025
Salary: $104000 per year

Sr. ASIC Design Verification Engineer, Kuiper Modem DV Team

verification environment to facilitate testing of the RTL against reference Matlab/C models · Develop detailed test plans... of FPGAs using test benches, which can be reused for the ASIC implementation · Run formal verification of complex blocks...

Company: Amazon
Location: Austin, TX
Posted Date: 04 Apr 2025
Salary: $143300 per year

Sr. ASIC Design Verification Engineer

a state of the art verification environment to facilitate testing of the RTL against reference Matlab/C models · Develop... · Participate in the validation of ASIC implementations in Verilog/SystemVerilog · Run formal verification of complex blocks...

Company: Amazon
Location: Austin, TX
Posted Date: 16 Mar 2025
Salary: $143300 per year

Design Verification Methodology Engineer - (UVM/SV)

covering design technology, functional verification technology, coverage, debug, low power technology, and automation... methodologies in the hardware design verification space. The following is a list of key responsibilities that the candidate...

Location: Austin, TX
Posted Date: 27 Feb 2025

Design Verification (DV) Engineer

performance verification. We are looking for experienced Design Verification (DV) engineers who are skilled at writing testbenches... and building verification environments to exercise complex HDL. Our ideal candidate is not only an ace tester, but a practicing...

Location: Austin, TX
Posted Date: 24 Jan 2025

Formal Verification Engineer

. Description As a formal verification engineer working the complete formal verification for single or multiple design blocks and IPs (CPU... center of a System-on-a-chip (SoC) design verification effort collaborating with design. Are you passionate about changing...

Company: Apple
Location: Austin, TX
Posted Date: 06 Apr 2025

Formal Verification Engineer

. Description As a formal verification engineer working the complete formal verification for single or multiple design blocks and IP's (CPU... center of a System-on-a-chip (SoC) design verification effort collaborating with design. Are you passionate about changing...

Company: Apple
Location: Austin, TX
Posted Date: 06 Apr 2025