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Keywords: Senior Verification Engineer, SoC, Location: Santa Clara, CA

Page: 1

Senior Principal Engineer, Verification (Ethernet, Serdes, UVM)

a highly skilled and experienced Senior Principal Verification Engineer to join our dynamic team in Santa Clara, CA. The ideal.... As a Senior Principal Verification Engineer, you will play a critical role in ensuring the quality and reliability of our cutting...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 28 Feb 2025

Senior Verification Engineer - Hardware

NVIDIA is looking for a Verification Engineer to join our Emulation division. We are a worldwide recognized division...-down design, SoC and system level verification. NVIDIA is on the move and our technology and vision position us as one of the...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 28 Feb 2025

Senior IP Design Verification Engineer

but not limited to: Oversees definition, design, verification, and documentation for SoC (System on a Chip) development... Logic design for integration of cell libraries, functional units and subsystems into SoC full chip designs, Register...

Company: Intel
Location: Santa Clara, CA
Posted Date: 19 Feb 2025

Sr. Staff Physical Verification CAD Engineer

and EDA Tools team is seeking a highly skilled and experienced Senior Staff Level Physical Verification CAD Engineer... interface activities, physical verification CAD flow, and CAD flows for SOC integration. Develop and maintain validation...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 18 Jan 2025
Salary: $113480 - 170000 per year

DDR Verification Engineer - Technical Lead

-edge server SOC. This individual will be responsible for driving the formal verification efforts of DDR interfaces..._ THE ROLE: We are looking for an experienced DDR Verification Expert to join our team as a Technical Lead for cutting...

Posted Date: 02 Mar 2025

SoC Design Engineer

We seek a skilled front-end SoC design engineer. A customer driven professional with a track record of effective...; Machine-learning, AI; FPGA. Title: Engineer (mid-senior career) Location: Santa Clara, CA. Hybrid. Relocation assistance...

Posted Date: 21 Feb 2025

Senior ASIC Infrastructure Engineer

We are now looking for a Senior Infrastructure Engineer! NVIDIA is looking to tap onto AI to define next generation... of chip design ! NVIDIA is seeking a passionate, highly motivated, and creative senior software engineer to be part of its CPU...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 26 Feb 2025

Senior E/E & Semiconductor Engineer - Digital Design (RTL) Engineer

Job Role: RTL Engineer Job Location: Santa Clara CA Job description: We are seeking Digital Design (RTL) engineer... developing designs from scratch. Experience applying linting and other (QC) quality checking and basic verification of designs...

Company: Capgemini
Location: Santa Clara, CA
Posted Date: 29 Jan 2025

Senior Staff Physical Design Engineer

closure, and signal integrity, and physical verification, ensuring robust, reliable, and high-speed SoC designs... across Marvell’s System-on-Chip (SoC) portfolio. This team supports the physical design needs of multiple SoC design groups...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 13 Dec 2024
Salary: $121840 - 182500 per year

Senior IP Logic Design Engineer

through clean design partitioning, clear microarchitectural documentation, reviewing RTL design and verification of features... correct interactions between blocks or Ips Reviews the verification plan and implementation to ensure design features...

Company: Intel
Location: Santa Clara, CA
Posted Date: 19 Feb 2025

ASIC/RTL Design Engineer - Senior (US)

of leading edge SoCs in advanced digital CMOS processes. Our RTL Design Engineers are expected contribute in all aspects of SoC..., Conversion of micro-architectural specifications to logic implementation, Verification, emulation, debug, synthesis, and timing...

Company: Managed Staffing
Location: Santa Clara, CA
Posted Date: 14 Feb 2025

ASIC/RTL Design Engineer - Senior (US)

of leading edge SoCs in advanced digital CMOS processes. Our RTL Design Engineers are expected contribute in all aspects of SoC..., Conversion of micro-architectural specifications to logic implementation, Verification, emulation, debug, synthesis, and timing...

Company: Managed Staffing
Location: Santa Clara, CA
Posted Date: 13 Feb 2025

Digital Design Engineer, Senior Staff

techniques and best practices Work with the physical design teams for synthesis and timing signoff. Work with the Verification... team on pre-silicon verification tasks such as reviewing the verification test plan, coverage analysis, and full-chip...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 16 Jan 2025
Salary: $124160 - 186000 per year