to join us in shaping the future. What you will be responsible for: Apply UVM (Universal Verification Methodology), SystemVerilog..., Verilog, and SVA (SystemVerilog Assertions) languages in verification tasks Develop and implement state-of-the-art...
As design verification engineer, you would be part of a passionate verification team that is constantly pushing the... limits – developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities...
such as PLL, DLL, ADC, regulators, amplifiers, TX, RX, CDRs etc. to meet key performance targets Performing design verification... in nanometric technologies and be able to supervise physical design. Be able to work in the lab independently or with test...