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Keywords: Senior Clocks Methodology Engineer, Location: Santa Clara, CA

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Senior Clocks Methodology Engineer

ASIC Methodology engineer with proven experience in high-speed logic design and verification. In order to support high..., to amplify human creativity and intelligence. Make the choice to join us today. The NVIDIA Clocks group is looking for a top...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 22 Oct 2024

Senior DFD Methodology Engineer

We are now looking for a Senior DFT Engineer! NVIDIA has continuously reinvented itself over two decades... in test access mechanisms which include scan dump, array dump, and JTAG methodology. Develop and deploy DFD...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 28 Aug 2024

Senior DFT Methodology Engineer

, to amplify human imagination and intelligence. Make the choice to join us today. DFX Methodology Group at NVIDIA works... including RTL & clocks design, STA, place-n-route and power. Experience in Silicon debug and bring-up on the ATE or SLT...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 29 Aug 2024

Senior ASIC Timing Engineer

, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic..., and/or full chip level. Work with PD, DFX, Clocks, and other teams in coming up with timing closure strategy, creating timing...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 12 Sep 2024

Senior DFX Architect

architecture and methodology that will enable NVIDIA GPUs, custom processors and accelerators to excel in quality and meet safety... including RTL, DFT, clocks, performance and power. Excellent analytical skills in verification and validation of logic...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 24 Aug 2024