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Keywords: Senior ASIC Timing Engineer, Location: Santa Clara, CA

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Senior ASIC Timing Engineer

, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic.... What you'll be doing: Drive timing analysis and closure of Nvidia’s GPUs, CPUs, DPUs and SoCs at block level, cluster level...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 19 Mar 2025

Senior High-Performance ASIC Timing Engineer

+ years’ experience in ASIC Design and Timing Hands-on experience in STA tools, ECO implementation, and timing closure.... What you'll be doing: Develop and execute timing closure plans for NVIDIA's next generation of high-performance IPs for CPU, GPU...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 26 Mar 2025

Senior Timing Methodology Engineer

, to amplify human inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive... To See: MS (or equivalent experience) in Electrical or Computer Engineering with 3 years’ experience in ASIC Design and Timing...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 17 Jan 2025

Senior ASIC Design Engineer

We are now looking for a Senior ASIC Design Engineer to join our System ASIC team! NVIDIA has continuously reinvented... in ASIC design flow including RTL design, verification, logic synthesis and timing analysis Strong coding skills in Perl...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 20 Mar 2025

Senior ASIC Design Engineer - Memory Controller

We are now looking for a Senior ASIC Design Engineer for Memory Controllers. As a Senior Designer at NVIDIA, you'll...-architecture and design including RTL design, synthesis, functional verification and timing analysis using groundbreaking CAD tools...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 15 Feb 2025

Senior ASIC Design Engineer (NetSec)

engineer on the ASIC team, you will create complex digital logic for our groundbreaking next-generation firewall products... Ensure that designs meet aggressive goals for area, timing, power, and testability in close collaboration with ASIC physical...

Location: Santa Clara, CA
Posted Date: 20 Mar 2025
Salary: $148000 - 180000 per year

Senior ASIC Design Engineer (NetSec)

engineer on the ASIC team, you will create complex digital logic for our groundbreaking next-generation firewall products... Ensure that designs meet aggressive goals for area, timing, power, and testability in close collaboration with ASIC physical...

Location: Santa Clara, CA
Posted Date: 19 Mar 2025
Salary: $148000 - 180000 per year

Senior ASIC Physical Design Engineer, Netlisting

, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Physical Design Engineer, Netlisting... checks, etc. Help in all aspects of physical design, such as driving timing convergence, timing constraints generation...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 23 Feb 2025

ASIC/RTL Design Engineer - Senior (US)

, Conversion of micro-architectural specifications to logic implementation, Verification, emulation, debug, synthesis, and timing...; - Knowledge AND hand-on experience from industry ASIC design flow including RTL coding, IP Integration, debugging/verification...

Company: Managed Staffing
Location: Santa Clara, CA
Posted Date: 14 Feb 2025

ASIC/RTL Design Engineer - Senior (US)

, Conversion of micro-architectural specifications to logic implementation, Verification, emulation, debug, synthesis, and timing...; - Knowledge AND hand-on experience from industry ASIC design flow including RTL coding, IP Integration, debugging/verification...

Company: Managed Staffing
Location: Santa Clara, CA
Posted Date: 13 Feb 2025

Senior Signal and Power Integrity Engineer

We are now looking for a Senior Signal & Power Integrity Engineer! NVIDIA has continuously reinvented itself over two..., and post layout PI extractions. Opportunity to work in a dynamic cross-functional role to optimize package, PCB, ASIC, mixed...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 15 Mar 2025

Senior Signal Integrity Design Engineer

We are now looking for a Senior Signal Integrity Design Engineer! NVIDIA has continuously reinvented itself over two... to optimize package, PCB, ASIC, SerDes designs. What we need to see: BS/MS-Electrical Engineering or equivalent experience 3...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 23 Jan 2025

Senior System Performance and Power Engineer

is seeking a versatile engineer to be part of the HW ArchDev team. The SSG team is uniquely positioned to have an end-to-end view... with architecture, ASIC, board/platform design, software/firmware, marketing, and other cross-functional teams to drive architecture...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 21 Mar 2025

Senior System Performance and Power Engineer

is seeking a versatile engineer to be part of the HW ArchDev team. The SSG team is uniquely positioned to have an end-to-end view... with architecture, ASIC, board/platform design, software/firmware, marketing, and other cross-functional teams to drive architecture...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 15 Mar 2025

Senior System Power Management Engineer

to amplify human inventiveness and intelligence. NVIDIA Silicon Solutions Group seeks a versatile engineer to join a Silicon HW.... Experience with ASIC power-saving features, system-level power-saving features, and experience optimizing products deploying...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 04 Jan 2025

CXLCM micro-Architect/Senior Logic Design Engineer

, come join us to do something wonderful. The IP Engineering Group is looking for energetic and passionate senior Design leaders to work closely... with established ASIC design team for advanced digital IO controller (like PCIe, UPI, CXL, IOMMU etc.) IP implementation on cutting...

Company: Intel
Location: Santa Clara, CA
Posted Date: 21 Mar 2025

Digital Design Engineer, Senior Staff

techniques and best practices Work with the physical design teams for synthesis and timing signoff. Work with the Verification... with focus on front-end complex RTL design Programming skills in Verilog Must be familiar with all stages of the ASIC design...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 16 Jan 2025
Salary: $124160 - 186000 per year

SoC Design Engineer

; Machine-learning, AI; FPGA. Title: Engineer (mid-senior career) Location: Santa Clara, CA. Hybrid. Relocation assistance...We seek a skilled front-end SoC design engineer. A customer driven professional with a track record of effective...

Posted Date: 21 Feb 2025