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Keywords: RTL Verification Engineer, Location: Bangalore, Karnataka

Page: 5

Principal ASIC Design Engineer

develop these systems. As a member of the design team, you will be involved in the specification, design and verification... to requirements/functions Work with architecture and other cross functional teams like Firmware, verification and emulation teams...

Company: Infinera
Posted Date: 21 Dec 2024

Senior Engineer - Design

in Infinera's systems. A dedicated team of 70 ASIC engineers gets to own and work on the Architecture, Design, Verification... of seasoned Engineers and fresh college graduates. Verification, emulation, platform experts who develop SW and FW Infinera...

Company: Infinera
Posted Date: 21 Dec 2024

VLSI Engineer

Verilog (UVM/OVM), RTL verification, languages (HDL/ HVL) - Competent to Expert Competency Levels Foundation... functionalities, architecture, layout and implementation for a client Do Conduct verification of the module/ IP functionality...

Company: Wipro
Posted Date: 20 Dec 2024

VLSI Engineer

Verilog (UVM/OVM), RTL verification, languages (HDL/ HVL) - Competent to Expert Competency Levels Foundation... functionalities, architecture, layout and implementation for a client Do Conduct verification of the module/ IP functionality...

Company: Wipro
Posted Date: 20 Dec 2024

MTS Silicon Design Engineer

: Feature Test plan creation, Verification of the IP in RTL, Gatesim and Analog Mixed Signal simulations. Create methodology... advantage. UPF based RTL low power verification ACADEMIC CREDENTIALS: Bachelor or Masters degree in ECE/EEE desired...

Posted Date: 18 Dec 2024

VLSI Engineer

Verilog (UVM/OVM), RTL verification, languages (HDL/ HVL) - Competent to Expert Competency Levels Foundation... functionalities, architecture, layout and implementation for a client Do Conduct verification of the module/ IP functionality...

Company: Wipro
Posted Date: 18 Dec 2024

VLSI Engineer

processes - Competent Technical Knowledge - Knowledge of System Verilog (UVM/OVM), RTL verification, languages (HDL/ HVL... Do Conduct verification of the module/ IP functionality and provide customer support Understand the architecture of the module...

Company: Wipro
Posted Date: 18 Dec 2024

DFT Engineer

Job Requirements Integration and Verification of MBIST at RTL level. RTL Integration, Verification, gate level...

Company: Quest Global
Posted Date: 16 Dec 2024

STA engineer (full chip)

(PrimeTime – SI), EM/IR-Drop analysis (PT-PX, Redhawk), Physical Verification (Calibre). Required Skills (Technical... development for netlist, RTL and timing level changes. Scripting experience in Perl/TCL · Excellent debugging skills...

Company: Quest Global
Posted Date: 16 Dec 2024

STA engineer (full chip)

(PrimeTime – SI), EM/IR-Drop analysis (PT-PX, Redhawk), Physical Verification (Calibre). Required Skills (Technical... development for netlist, RTL and timing level changes. Scripting experience in Perl/TCL · Excellent debugging skills...

Company: Quest Global
Posted Date: 16 Dec 2024

Trainee Engineer - PD

) optimized design. Work closely with the cross-functional team of Verification, Design for Test, Physical Design and Software... design document such as interface protocol, block diagram, transaction flow, pipeline, etc. Perform RTL coding for SS/SoC...

Company: Quest Global
Posted Date: 16 Dec 2024

CPU emulation - Zebu - SDE/MTS/SMTS Silicon Design Engineer

, debugging emulation issues of RTL, giving feedback to design team for latest gen CPU in pre-silicon and emulation environment... techniques PREFERRED EXPERIENCE: Experience: 3-15 years' experience in processor/ASIC design verification. Experience...

Posted Date: 12 Dec 2024

Principal Physical Design Engineer

with the RTL design team to drive modifications that address congestion and timing issues. Collaboration with the frontend... and projects that involved circuit design, testing, and timing analysis. Good understanding of standard RTL to GDS flows...

Company: Marvell
Posted Date: 06 Dec 2024

ASIC Design Engineer (Staff) - Peripheral

like USB/PCIE/Ethernet preferred. Work closely with the SoC verification and validation teams for pre/post Silicon debug... is a plus. Strong experience in micro architecting RTL design from high level design specification. Excellent problem solving skills...

Company: Qualcomm
Posted Date: 27 Nov 2024

Senior Digital Design Engineer

at different stages – RTL/ constraints/ CDC waivers, timing wavers, DFT DRCs and waivers, software programming sequence... of Design Verification (DV) practice, ease of integration and make recommendations Build expertise on complex interfaces...

Posted Date: 19 Nov 2024

Digital Design Engineer

into design flow at different stages – RTL/ constraints/ CDC waivers, timing wavers, DFT DRCs and waivers, software programming... For Testability, robustness of Design Verification (DV) practice, ease of integration and make recommendations Build expertise...

Posted Date: 13 Nov 2024

NoC Systems Engineer

and preparing specification for interconnect working with adjacent IPs Actively work with QPA team, SoC team, verification team..., QNoC changes and Low Power Technology changes to guide and influence the NoC Design, Verification, Power and Physical...

Company: Qualcomm
Posted Date: 01 Nov 2024

SMTS Silicon Design Engineer AECG ASIC DV Lead

_ THE ROLE: The focus of this role is to plan, build, and execute the verification of new and existing features for AMD... processor architecture, digital design, and verification in general. You are a team player who has excellent communication...

Posted Date: 24 Oct 2024

Senior Staff Physical Design Engineer

with the RTL design team to drive modifications that address congestion and timing issues. Collaboration with the frontend... of standard RTL to GDS flows and methodology, experience in designing ICs at advanced technology nodes (e.g., 7nm, 5nm...

Company: Marvell
Posted Date: 17 Oct 2024

Full chip SoC timing lead

_ SMTS SILICON DESIGN ENGINEER THE ROLE: As a member of the Strategic Silicon Solution Group Full Chip Physical Design..., Synthesis, Logical equivalence, Physical Verification, Power design/implementation/signoff, and will act as a mentor/coach/guide...

Posted Date: 28 Dec 2024