Find your dream job now!

Click on Location links to filter by Job Title & Location.
Click on Company links to filter by Company & Location.
For exact match, enclose search terms in "double quotes".

Keywords: RTL Digital Design Engineer, Location: San Jose, CA

Page: 1

RTL Digital Design Engineer

and quality THE PERSON: We are looking for a RTL digital design engineer to join the FPGA Architecture Development group. The..._ THE ROLE: Building full-chip RTL connectivity models. Integrating RTL components from multiple design teams. Verifying...

Posted Date: 07 Feb 2025

ASIC/RTL Design Engineer - Senior

. Job Title: ASIC/RTL Design Engineer - Senior Work Location: San Jose, CA, 95124 Duration: 7 Months Work Type: Contract..., and participating in, the design of leading edge SoCs in advanced digital CMOS processes. Our RTL Design Engineers are expected...

Company: TekWissen
Location: San Jose, CA
Posted Date: 06 Feb 2025

Senior RTL Design Engineer

of experience as a Digital Design Engineer and experience in RTL coding, synthesis, and/or SoC integration Familiarity with digital.... Embedded services: device drivers, RTOS porting, Board bring up. Prodapt is looking for a Senior RTL Design Engineer who...

Company: Prodapt
Location: San Jose, CA
Posted Date: 15 Jan 2025

Digital Design Engineer

expertise in RTL design, synthesis, and design optimization to drive the development of high-performance digital systems... Expertise: Lead the design and implementation of advanced digital blocks and subsystems. Provide domain expertise in RTL...

Company: Broadcom
Location: San Jose, CA
Posted Date: 19 Dec 2024
Salary: $119000 - 190000 per year

Principal Digital SOC Engineer

Responsibilities: MaxLinear is seeking a Principal Digital SOC Engineer to join our Analog Mixed Signal (AMS) Design... in Digital ASIC implementation at subsystem level or chip level including RTL and test bench design skills using Verilog, System...

Company: MaxLinear
Location: San Jose, CA
Posted Date: 20 Jan 2025
Salary: $134300 - 208495 per year

Physical Design Engineer

. Your Impact As a physical design engineer you will be spearheading the implementation of complex multi-hierarchy designs...). Experience and knowledge of hardware architecture and RTL/logic design for timing closure, specifically experience in critical...

Company: Cisco Systems
Location: San Jose, CA
Posted Date: 01 Feb 2025
Salary: $133300 - 186800 per year

Senior/Principal Datapath Design Engineer

: Join Micron Technology as a Principal Datapath Design Engineer in the Non-Volatile Engineering Group in San Jose, CA... and excellence. Responsibilities: Design, analyze, and optimize digital and analog circuits for new memory products, ensuring...

Company: Micron
Location: San Jose, CA
Posted Date: 26 Jan 2025

ASIC Design Engineer

networks that generate billions in service revenue for our customers. Title: ASIC Design Engineer Location: San Jose, CA... spec / micro-architecture and RTL development · Design size/timing/power optimization via micro-architecture/RTL...

Company: Infinera
Location: San Jose, CA
Posted Date: 20 Dec 2024

IC Design Engineer

Job Description: IC Design Engineer Participate in IP level architectural definition including micro-architecture... definition Perform RTL design using Verilog HDL, with an emphasis on performance and area Implement multi-power and low...

Company: Broadcom
Location: San Jose, CA
Posted Date: 15 Dec 2024
Salary: $119000 - 190000 per year

Silicon Design Verification Engineer

: You have a passion for digital design, and verification in general. You are a team player who has excellent communication skills... Define test plans, test benches, and tests using System Verilog and UVM Debug RTL and Gate simulations and work with HW...

Posted Date: 20 Jan 2025

Senior Design Verification (DV) Engineer

-chip/system simulation, and performance analysis. Who You'll Work With You will work with front-end RTL Design... 2,100 employees across 16 countries, we design the networking hardware for Enterprises and Service Providers of various sizes, the...

Company: Cisco Systems
Location: San Jose, CA
Posted Date: 07 Jan 2025

Senior ASIC Design Engineer

and design RTL coding in Verilog/SystemVerilog Low power RTL design techniques, UPF methodology Design flow quality checks... design and Verilog/SystemVerilog RTL Active knowledge of all aspects of ASIC and FPGA design flows Low power analysis...

Posted Date: 14 Nov 2024

Design Engineering Intern (Summer 2025)

Engineer at a world leader in computational software, semiconductor design IP, and system verification hardware. Our customers... with various RTL Design and Electronic Design Automation teams. Position Requirements: Currently pursuing MS/BS in Electrical...

Posted Date: 07 Feb 2025

ASIC Design Technical Leader - Design & Timing Constraints Focus

You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding of timing constraints, including clock... timing in multiple timing modes. Option to also do block level RTL design or block or top-level IP integration. Helping...

Company: Cisco Systems
Location: San Jose, CA
Posted Date: 12 Dec 2024

Principal System Engineer

team in the SerDes IP R&D Group at Cadence Design Systems. We are looking for a Principal System Engineer who will be a key... Knowledge and experience with SOC design tools such as Digital and Analog simulations, a static timing analysis, physical...

Posted Date: 02 Feb 2025

Sr. Hardware Development Engineer

_ THE ROLE: AMD-Xilinx is seeking an Entry Level SOC Design Engineer to be part of Front End SOC Design Team..., you will implement functions in RTL, integrate IP from internal and external sources, ensure quality and get design ready for synthesis...

Posted Date: 25 Jan 2025

Lead Application Engineer SCBU

with EDA tools on layout, STA, Extraction-SPEF/DSPF, Spice, IC/ASIC design flow experience from RTL to GDSII, custom circuit... to know how their world-changing ideas will perform, they close the gap between design and reality with Ansys simulation...

Company: Ansys
Posted Date: 17 Jan 2025