, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact This position is with ASIC design..., Timing, PV and Power implementation all custom ASICs for all the OEM’s, CSSP’s. We are looking for strong technical leaders...
, collaborating closely with the RTL design team to drive modifications that address congestion and timing issues. Collaboration... electronics, CMOS design and projects that involved circuit design & analysis. Good understanding of standard RTL to GDS flows...
for doing placement, CTS, and routing. Work closely with RTL design and DFT teams to understand design requirements... with low-power design techniques and methodologies, such as multi-voltage domains and power gating using UPF. Expertise...
_ MANAGER – SILICON DESIGN ENGINEER THE ROLE: AMD seeks a passionate, collaborative leader with strong technical skills.... Experience in clocking, reset, power-up sequences and power management verification. Understanding of low power design...
_ SENIOR MANAGER SILICON DESIGN ENGINEER THE ROLE: The ideal candidate will get to work on Verification of complex Analog... verification methodology is an added advantage. UPF based RTL low power verification Prior experience in working on IPs...
and analog/mixed-signal products. As Senior Principal / Staff Engineer, you will define the design platform, targeting a large... variety of different products. Your responsibilities will include architecture definition, design specification, RTL modeling...
-signal products. As Senior Principal / Staff Engineer, you will define the design platform, targeting a large variety... of different products. Your responsibilities will include architecture definition, design specification, RTL modeling...
motivated Staff design engineer who will be responsible for design and development of RTL for Machine Learning engine... and 5 years for PHD) experience in RTL design Independent and self-motivated, capable of executing under dynamic...
a STA/Timing Engineer to join the HW design team focused on IP design and full chip integration. This position... chip timing and bring best-in-class methodologies to achieve best power, performance, and area. Ensuring design quality...
of the architecture team. Collaborate with cross functional teams working on RTL design, Design Verification, Firmware..., team or location ASIC Engineer, SoC Architect (AI Accelerators) Responsibilities Work on modeling, performance analysis...
with other R&D teams such as RTL, DFT, digital IP, PD, Design Enablement, Emulation, and Validation to achieve project milestones.... We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘To Make...
with other R&D teams such as RTL, DFT, digital IP, PD, Design Enablement, Emulation, and Validation to achieve project milestones.... We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘To Make...
Build strong collaboration with other R&D teams such as RTL, DFT, digital IP, PD, Design Enablement, Emulation... into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities...
Build strong collaboration with other R&D teams such as RTL, DFT, digital IP, PD, Design Enablement, Emulation... into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities...
with other R&D teams such as RTL, DFT, digital IP, PD, Design Enablement, Emulation, and Validation to achieve project milestones.... We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘To Make...
Build strong collaboration with other R&D teams such as RTL, DFT, digital IP, PD, Design Enablement, Emulation... into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities...
at IP, subsystem and SOC level.You will collaborate with digital and analog architects, RTL developers, and physical design...) is looking for a Pre-Silicon Verification Engineer to deliver latest and best-in-class DDR PHY IP for SoCs across Intel for the latest...
Engineer to join the HW design team focused on IP design and full chip integration. This position is an opportunity to be part... methodologies to achieve best power, performance, and area. Ensuring design quality through timing validation quality checks...
design Implementation RTL to GDSII : Synopsys/Cadence tools. Familiar with LVF/POCV variation formats and understanding... Client SOCs. We envision the future of computing and design for the next generation of laptop and desktop computers...
with cross-functional engineering teams. In this position, the engineer will be involved in all stages of the design..., IO budgeting for blocks Logical equivalence check between RTL to Netlist and Netlist to Netlist Knowledge of low-power...