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Keywords: PLL Design Engineer, Location: Santa Clara, CA

Page: 1

PLL Design Engineer

_ THE ROLE: We are looking for an adaptive, self-motivative logic design engineer to join our growing PLL team. As a key...: Proven experience in analog mixed-signal design from specification to successful silicon experienced in PLL, High Speed...

Posted Date: 29 Mar 2025

PLL Design Engineer

_ THE ROLE: AMD is searching for an experienced Circuit Design Engineer to join the fast-growing PLL design team... of complex building blocks of a PLL including architecture development and transistor level circuit design Run pre-tapeout...

Posted Date: 23 Mar 2025

Principal Analog Mixed Signal IC Design Engineer

, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As an Analog IC Design Principal... Engineer with Marvell, you’ll be a member of the Central Engineering business group. If you picture Marvell as a wheel, Central...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 25 Mar 2025
Salary: $165630 - 248100 per year

Senior Principal Analog Design Engineer

in one or more of the following focus areas of analog design: ADC/DACs, Front-Ends, CTLE, PLL, Timing circuits, CDRs, SerDes. Ability..., above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As a Senior Principal Analog Design...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 28 Feb 2025

Senior Staff Analog Mixed Signal IC Design Engineer

and beyond. Design IP that includes but not limited to 224G/112G/56G PAM4; 32G PAM2; Die-to-Die High Speed Interconnect; System PLL IPs..., above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As an Analog IC Design Principal...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 21 Feb 2025
Salary: $140350 - 210200 per year

Analog Design, Senior Staff Engineer

, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As an Analog Design Engineer... of innovation in the field of High Speed SerDes Links. What You Can Expect As an analog circuit design engineer...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 02 Feb 2025
Salary: $128160 - 192000 per year

Senior Photonic Layout Design Engineer

Are you seeking an outstanding opportunity? We are looking for a Senior Photonic Layout Design Engineer – someone who... chip layout circuit design, circuit checking, and device evaluation and characterization. Responsible for chip floorplan...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 31 Jan 2025

Senior Mixed-Signal Design Engineer

Design Engineer. As a member of our Mixed-Signal team, you will be leading architecture definition and design of CMOS high... interpersonal skills Validated experience in leading and mentoring designers Your extensive design experience in PLL and high...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 25 Jan 2025

Staff System Design Engineer

functionality. What You Can Expect As a Hardware and Silicon Validation Staff Engineer at Marvell, you’ll be helping to deliver... to ensure product’s quality. Characterize electrical parameters and building blocks such as Tx jitters, CDR loops, CTLE, PLL...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 16 Feb 2025
Salary: $102880 - 154100 per year

Senior Mixed Signal Design Engineer

needle! As a member of our Mixed Signal team, you will lead the design of CMOS high-speed interface circuits and mixed-signal.... What you'll be doing: Lead design and implementation of high speed interface circuit Design projects include high speed...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 14 Mar 2025

Sr. Analog Mixed-Signal Design Engineer

, FIFO, CDR, PLL etc. Design and debug experience on RTL level signal synchronization, clock tree and cross domain clock...Responsible for the design development and characterization of embedded analog circuits, such as high speed I/O, SerDes...

Company: OmniVision
Location: Santa Clara, CA
Posted Date: 16 Feb 2025
Salary: $120000 - 155000 per year

Analog Mixed-Signal Design Engineer

, FIFO, CDR, PLL etc. Design and debug experience on RTL level signal synchronization, clock tree and cross domain clock...Responsible for the design development and characterization of embedded analog circuits, such as high speed I/O, SerDes...

Company: OmniVision
Location: Santa Clara, CA
Posted Date: 16 Feb 2025
Salary: $105000 - 135000 per year

Analog IC Design, Principal Engineer

budget, behavioral modeling, and transistor-level feasibility. You will also drive schematic design and collaborate on mask... design for implementation. And finally, with the team, you will drive designs into volume production and delight customers...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 16 Feb 2025
Salary: $165630 - 248100 per year

Staff Silicon Validation Engineer

considerations and PLL/DLL/CDR/ADC/DAC architectures. Experience in high-speed I/O design and testing, particularly with electrical...'s internal IPs, such as High-Speed SerDes, PLL/DLL, and ADCs. Feature Evaluation and Firmware Development: Assess and debug new...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 20 Feb 2025
Salary: $102880 - 154100 per year