Find your dream job now!

Click on Location links to filter by Job Title & Location.
Click on Company links to filter by Company & Location.
For exact match, enclose search terms in "double quotes".

Keywords: Memory RTL Design Engineer, Location: Santa Clara, CA

Page: 1

Memory RTL Design Engineer

_ THE ROLE: The Memory PHY team is looking for a passionate and experienced Design Engineer for RTL and Firmware... development of high-speed LPDDR, DDR IPs. Be a part of the definition, design and development phase of industry-leading Memory...

Posted Date: 18 Dec 2024

CPU RTL Engineer

to contribute to architecture and RTL development for our future CPU designs. Description Description As a CPU RTL Engineer... - development, assessment and refinement of RTL design to target power, performance, area and timing goals. • Verification - support...

Company: Apple
Location: Santa Clara, CA
Posted Date: 09 Oct 2024
Salary: $121900 - 183600 per year

CPU Cache Microarchitect/RTL Engineer

. Description Description As a CPU Cache Microarchitect/RTL Engineer, you will own or participate in the following: • Micro-architecture development... specification. • RTL ownership - development, assessment and refinement of RTL design to target power, performance, area and timing...

Company: Apple
Location: Santa Clara, CA
Posted Date: 09 Oct 2024

CPU Microarchitect/RTL Engineer - Execution, Load/Store

, Vision Pro, and Mac. We are looking for an experienced engineer to drive architecture and RTL development of CPU integer... ownership - development, assessment and refinement of RTL design to target power, performance, area and timing goals...

Company: Apple
Location: Santa Clara, CA
Posted Date: 09 Oct 2024

CPU Power Management Microarchitect/RTL Engineer

power management solutions. Description Description As a CPU Power Management Microarchitect/RTL Engineer, you will own... and refinement of RTL design to target power, performance, area and timing goals. • Verification - support the verification team...

Company: Apple
Location: Santa Clara, CA
Posted Date: 09 Oct 2024

CPU Power Management Microarchitect/RTL Engineer

power management solutions. Description Description As a CPU Power Management Microarchitect/RTL Engineer, you will own... and refinement of RTL design to target power, performance, area and timing goals. • Verification - support the verification team...

Company: Apple
Location: Santa Clara, CA
Posted Date: 09 Oct 2024

CPU Cache Microarchitect/RTL Engineer

. Description Description As a CPU Cache Microarchitect/RTL Engineer, you will own or participate in the following: • Micro-architecture development... specification. • RTL ownership - development, assessment and refinement of RTL design to target power, performance, area and timing...

Company: Apple
Location: Santa Clara, CA
Posted Date: 09 Oct 2024

CPU Microarchitect/RTL Engineer - Execution, Load/Store

, Vision Pro, and Mac. We are looking for an experienced engineer to drive architecture and RTL development of CPU integer... ownership - development, assessment and refinement of RTL design to target power, performance, area and timing goals...

Company: Apple
Location: Santa Clara, CA
Posted Date: 08 Oct 2024

CPU Cache Microarchitect/RTL Engineer

. Description Description As a CPU Cache Microarchitect/RTL Engineer, you will own or participate in the following: • Micro-architecture development... specification. • RTL ownership - development, assessment and refinement of RTL design to target power, performance, area and timing...

Company: Apple
Location: Santa Clara, CA
Posted Date: 08 Oct 2024
Salary: $121900 - 183600 per year

GPU Design Engineer - Memory Hierarchy

! Description Description As a GPU Design Engineer, you will participate in micro-architecture specification and RTL coding. Explore architecture trade.... Join us to help deliver the next groundbreaking products containing an Apple designed GPU. As part of the GPU Memory Hierarchy Design...

Company: Apple
Location: Santa Clara, CA
Posted Date: 26 Oct 2024
Salary: $121900 - 183600 per year

GPU Design Engineer - Memory Hierarchy

! Description Description As a GPU Design Engineer, you will participate in micro-architecture specification and RTL coding. Explore architecture trade.... Join us to help deliver the next groundbreaking products containing an Apple designed GPU. As part of the GPU Memory Hierarchy Design...

Company: Apple
Location: Santa Clara, CA
Posted Date: 25 Oct 2024

ASIC Design Engineer - Memory Cache Controller

, and power consumption along with the performance analysis team. Develop/debug RTL design of different sections of the cache... Qualifications Key Qualifications Development of memory systems. Experience in RTL/micro-architecture definition. Experience...

Company: Apple
Location: Santa Clara, CA
Posted Date: 08 Nov 2024

GPU Design Engineer - Memory Hierarchy

. Join us to help deliver the next groundbreaking products containing an Apple designed GPU. As part of the GPU Memory Hierarchy Design... help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You'll...

Company: Apple
Location: Santa Clara, CA
Posted Date: 26 Oct 2024

ASIC Design and Integration Engineer

in ASIC design with: - Architecture research and/or development of memory or highly interconnected system architectures. - RTL.../micro-architecture. - Knowledge of high-performance memory subsystem, including dram controller, PHY architecture and design...

Company: Apple
Location: Santa Clara, CA
Posted Date: 22 Dec 2024
Salary: $121900 - 183600 per year

ASIC Design Engineer

NVIDIA is looking for an ASIC Design Engineer to join our Memory Subsystem Team! As an ASIC Design engineer at NVIDIA... platforms of tomorrow. What you'll be doing: As a member of our Memory Subsystem Design team, you will collaborate...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 22 Dec 2024

Senior ASIC Design Engineer

We are now looking for a Senior ASIC Design Engineer to join our System ASIC team! NVIDIA has continuously reinvented.... What you’ll be doing: Be an integral part of the System ASIC Design team to help develop and improve our RTL and SOC designs...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 12 Dec 2024

ASIC Design and Integration Engineer

in ASIC design with: - Architecture research and/or development of memory or highly interconnected system architectures. - RTL.../micro-architecture. - Knowledge of high-performance memory subsystem, including dram controller, PHY architecture and design...

Company: Apple
Location: Santa Clara, CA
Posted Date: 15 Nov 2024
Salary: $121900 - 183600 per year

Graphics Cache Hierarchy Design Verification Engineer

Engineer will be responsible for the pre-silicon RTL verification of graphics memory subsystem units including Caches, Memory... help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You'll...

Company: Apple
Location: Santa Clara, CA
Posted Date: 26 Oct 2024
Salary: $121900 - 183600 per year

Graphics Cache Hierarchy Design Verification Engineer

Engineer will be responsible for the pre-silicon RTL verification of graphics memory subsystem units including Caches, Memory... help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You'll...

Company: Apple
Location: Santa Clara, CA
Posted Date: 26 Oct 2024

CPU Physical Design Engineer

design. Description Description As a CPU Physical Design Engineer, you will drive or participate in the following...: • Drive RTL-to-GDS design convergence through logic synthesis and place-and-route tools targeting ambitious PPA goals...

Company: Apple
Location: Santa Clara, CA
Posted Date: 18 Oct 2024