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Keywords: DFT Design Engineer -Memory Team, Location: Bangalore, Karnataka

Page: 2

Product Engineer - Physical Design

: Lead a Team of Engineers working on solving the latest design challenged in Logic Synthesis Can you collaborate with RnD...Job Description: Siemens EDA is a global technology leader in Electronic Design Automation software. Our software...

Company: Siemens
Posted Date: 09 Mar 2025

Graphics ASIC RTL Design Engineer- Sr Engineer /Sr Lead / Staff / Sr Staff

. The successful candidate for this position will specify and design digital blocks in our Multimedia Graphics team... design, test plan development, coverage-based design verification, and/or design-for-test (DFT) Experience with Computer...

Company: Qualcomm
Posted Date: 03 Feb 2025

RTL/Integration- Subsystem/IP Design Lead

_ SMTS SILICON DESIGN ENGINEER THE ROLE: As a member of the Computing and Graphics group, you will help bring to life... cutting-edge designs. As a member of the front-end design/integration team, you will work closely with the architecture, IP...

Posted Date: 23 Apr 2025

Technical Lead - Mixed Signal Design

-disciplinary team (Mechanical team for thermal analysis & enclosures design, PCB layout team and suppliers..., Transport, Aerospace and Digital Identity and Security markets. Technical Lead - Mixed Signal Design Thales India...

Company: Thales
Posted Date: 21 Mar 2025

CPU STA/Timing Engineer

Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical...+ years of Hardware Engineering or related work experience. As a Physical Design Timing Engineer, you will work...

Company: Qualcomm
Posted Date: 18 Apr 2025

Post Silicon Validation (ATE) Lead Engineer

., PCIe, DDR, Ethernet). Experience with design-for-test (DFT) methodologies and scan insertion....Job Requirements We are seeking a highly skilled Senior ATE Test Engineer with expertise in RMA (Return Material...

Company: Quest Global
Posted Date: 16 Apr 2025

Post Silicon Validation (ATE) Engineer

., PCIe, DDR, Ethernet). Experience with design-for-test (DFT) methodologies and scan insertion....Job Requirements We are seeking a highly skilled ATE Test Engineer with expertise in RMA (Return Material...

Company: Quest Global
Posted Date: 16 Apr 2025

Sr Staff Product Engineer

Job Description Analog and Connectivity Business Unit (A&C) is looking for a Staff Product Engineer to join our team... opportunity to work with a cross-functional team to bring a product to volume production starting from product conception...

Posted Date: 10 Apr 2025

Senior Engineer - Hardware

Senior Hardware Engineer to join our dynamic team, who will play a pivotal role in our engineering team, working.... What you will do: Play a key role in design and development of hardware solutions, often working as part of a larger team to ensure...

Company: Allegion
Posted Date: 10 Apr 2025

Sr Staff Product Engineer

and Connectivity Business Unit (A&C) is looking for a Staff Product Engineer to join our team to drive the product development of state... team to bring a product to volume production starting from product conception to production release. The job scope includes...

Posted Date: 10 Apr 2025

Principal Verification Engineer-Automotive SOC

Summary: The Digital Verification Engineer / Architect is responsible for defining Design Verification strategy, plan... across multiple global sites and manage verification deliverables - Collaborate closely with cross-functional teams: Design, DFT...

Posted Date: 10 Apr 2025

Mechanical Program Lead Engineer

The Group You'll Be A Part Of In the Global Products Group, we are dedicated to excellence in the design... the biggest challenges in the semiconductor industry. The Impact You'll Make As a Mechanical Engineer at Lam, you're...

Company: Lam Research
Posted Date: 10 Apr 2025

Lead PCB Engineer

We are looking for a Lead PCB Design Engineer who will drive the PCB design of our next-generation products. As the PCB..., Design for Manufacturability (DFM), Design for Testability (DFT), thermal management, and safety. Experience with processor...

Posted Date: 03 Apr 2025

STA Timing Engineer- 11+ years

_ SMTS SILICON DESIGN ENGINEER THE ROLE: The focus of this role will involve driving the physical design flow from timing...) targets on SerDes PHY IPs. THE PERSON: As a senior member of the SerDes IP Physical Design (PD) team, your primary...

Posted Date: 26 Mar 2025

Snr STA Engineer

Job Description: JD Physical design engineer is expected to take a digital design block through all phases of the... block development process from RTL2GDS, including synthesis, design for test (dft), place & route, extraction, timing...

Company: onsemi
Posted Date: 24 Mar 2025

ASIC Engineer, Implementation

in the same team in India for a minimum period of 24 months before being eligible for transfer to another role, team... or location. ASIC Engineer, Implementation Responsibilities Run Logic/Physical Synthesis using advanced optimization...

Company: Meta
Posted Date: 22 Mar 2025

ASIC Engineer, Front-End Implementation

, synthesis to build efficient System on Chip (SoC) and IP for data center applications. ASIC Engineer, Front-End Implementation... with the Designers to create waivers. Perform RTL DFT Analysis and improve the DFT coverage for Stuck-at faults. Develop...

Company: Meta
Posted Date: 14 Feb 2025

CPU STA/Timing Analysis Engineer (All Levels)

Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical.... As a Physical Design Timing Engineer, you will work with microarchitecture, RTL design, CAD, block level and top level physical...

Company: Qualcomm
Posted Date: 13 Feb 2025

Senior Engineer

Engineer (Digital) Experience : 5+ years Education : Bachelors/Masters engineering degree in Computer Science/Electrical.../Micro-Electronics Location : Bangalore (ADBL) Job Grade : P3 Responsibilities Develop and drive Design-for-Test...

Posted Date: 08 Feb 2025

SOC Full Chip Timing Engineer

to: Design and Architecture understanding, Interaction with FE/DFT/Verification teams, Clocking, Constraints development, ACIO... extraction issues, deciding timing signoff modes and corners, Design margins, Hierarchical timing including IO budgeting...

Company: Intel
Posted Date: 22 Apr 2025