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Keywords: ASIC Timing Engineer, Location: Cupertino, CA

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ASIC Timing Engineer

chain-of-thought reasoning. ASIC Timing Engineer Etched is seeking an exceptional ASIC Timing Engineer... to join our innovative team. The candidate will be responsible for driving timing analysis and closure of our next-generation AI chips...

Company: Etched
Location: Cupertino, CA
Posted Date: 20 Feb 2025
Salary: $2000 per month

Sr. Physical Design Engineer - Static Timing Analysis, Annapurna Labs, Cloud Scale Machine Learning

an experienced Sr. Physical Design STA Engineer to build the next generation of our cloud server platforms. Our success depends... beyond what is possible today. Key job responsibilities Develop & maintain flows for block and full-chip level static timing analysis Write, debug...

Company: Amazon
Location: Cupertino, CA
Posted Date: 24 Apr 2025
Salary: $143300 per year

Physical Design Engineer - Static Timing Analysis, Annapurna Labs, Cloud Scale Machine Learning

beyond what is possible today. Key job responsibilities Develop & maintain flows for block and full-chip level static timing analysis Write, debug... & validate timing constraints for blocks and full-chip. Run Static Timing Analysis and give frequent feedback to team members...

Company: Amazon
Location: Cupertino, CA
Posted Date: 24 Apr 2025
Salary: $129800 per year

ASIC Design Engineer - Pixel IP

a critical impact getting functional products to millions of customers quickly. Description As an ASIC Design Engineer in the... Verilog. Extensive shown experience in ASIC implementation, especially logic synthesis, static timing analysis, logic...

Company: Apple
Location: Cupertino, CA
Posted Date: 23 Apr 2025

ASIC Design Engineer - Pixel IP

a critical impact getting functional products to millions of customers quickly. Description As an ASIC Design Engineer in the... Verilog. Extensive shown experience in ASIC implementation, especially logic synthesis, static timing analysis, logic...

Company: Apple
Location: Cupertino, CA
Posted Date: 22 Apr 2025

ASIC Design Engineer - Pixel IP

Previous strong experience in media, video, pixel, or display designs. A good understanding of timing/area/complexity... of ASIC/FPGA design methodology Strong collaboration skills Outstanding written and verbal communication Pay & Benefits...

Company: Apple
Location: Cupertino, CA
Posted Date: 10 Apr 2025

ASIC Physical Design Engineer, Annapurna Labs

, power/clock distribution, timing optimization, place and route, power integrity analysis, and physical verification Write...

Company: Amazon
Location: Cupertino, CA
Posted Date: 24 Apr 2025
Salary: $104000 per year

RTL Design Engineer

chain-of-thought reasoning. RTL Design Engineer As an RTL Engineer at Etched, you will be critical in ensuring... and upcoming ASIC designs. In this role, you will work closely with state-of-the-art architectures for machine learning...

Company: Etched
Location: Cupertino, CA
Posted Date: 20 Feb 2025
Salary: $2000 per month

Physical Design Engineer

chain-of-thought reasoning. Physical Design Engineer Etched is looking for exceptional PD engineers to join our team... Design flows to close blocks, support ASIC infrastructure, automate Physical Design flows, improve CAD infrastructure Drive...

Company: Etched
Location: Cupertino, CA
Posted Date: 20 Feb 2025
Salary: $2000 per month

Circuit Design And Analysis, Annapurna Labs, Cloud Scale Machine Learning

in datacenters all around the world. As a Circuit & Design Analysis engineer, you'll collaborate with multiple teams to drive... Design & Analysis engineer with a background in custom circuit design & analysis, system level thermal & power analysis...

Company: Amazon
Location: Cupertino, CA
Posted Date: 24 Apr 2025
Salary: $143300 per year