Keywords: ASIC Design Engineer :: RTL Design | Verilog or System Verilog | Exp - 7+ Years, Location: Bangalore, Karnataka

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ASIC Design Engineer :: RTL Design | Verilog or System Verilog | Exp - 7+ Years

's Degree in Electrical or Computer Engineering with 7+ years of ASIC design. Prior experience working with Verilog or System... Verilog RTL to meet timing, performance, and power requirements. Contribute to full chip integration and timing methodology...

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Company: Cisco Systems

Location: Bangalore, Karnataka

Posted Date: 29 Jan 2025

ASIC Design Verification Engineer || UVM/System Verilog || Test benches || Exp 4 to 7 years

in emulation. Minimum Qualifications Bachelor's Degree in EE, CE, or other related fi eld. 5+ years of related ASIC design... verification experience. Proficient in ASIC verification using UVM/System Verilog. Proficient in verifying complex blocks...