Designers, towards completion of Analog Mixed Signal IPs. Description Description As a Static Timing Engineer..., you will be spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign-off, STA and sign-off flow...
, logic synthesis, timing constraints, timing closure, STA, back annotation of parasitics, gate level simulation, equivalence... creative RTL Design Engineer. As a part of our multifaceted group, you will have the rare and great opportunity to craft...