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Keywords: Timing Engineer, Location: Bangalore, Karnataka

Page: 8

Memory Team - Physical Design Engineer

and Route, STA , timing and physical signoffs Role and Responsibilities - Hands on experience doing physical design... and timing closure of complex blocks and full-chip designs - Should have strong understanding of timing, power and area trade...

Company: 삼성전자
Posted Date: 01 Oct 2024

Wifi MAC -Design Engineer -Sr Lead

-RTL to Netlist release, and converge on area, timing, power and testability Primary tasks include writing timing...

Company: Qualcomm
Posted Date: 29 Sep 2024

ASIC Engineer

with the micro-architecture, implement RTL, drive the verification, close timing, and support silicon validation. Developing... driven verification closure. Develop and enhance timing analysis/signoff work-flow from frontend (pre-layout) to backend...

Company: Nvidia
Posted Date: 29 Sep 2024

WLAN PHY Baseband (RTL) Digital design Engineer- Senior

, you will be responsible for identifying power/area/performance improvements and propose solutions for the same. Develop timing constraints..., working with implementation/PD teams in resolving any timing issues. Work closely with cross functional teams...

Company: Qualcomm
Posted Date: 29 Sep 2024

Sr Principal Digital Engineer

closely with functional verification teams on test-plan development and debug. Understand timing constraints, run synthesis...

Posted Date: 27 Sep 2024

CPU Design Verification - Sr Engineer

for all features and, debug of the test failures Hands-on experience of GLS and timing simulations Exposure to Formal verification...

Company: Qualcomm
Posted Date: 26 Sep 2024

CPU Design Verification - Staff Engineer

with understanding of UPF Handson experience of GLS and timing simulations Exposure to Formal verification Self-driven and motivated...

Company: Qualcomm
Posted Date: 26 Sep 2024

Wireless HW Synthesis Engineer

tasks include writing timing constraints, power-aware synthesis, power-aware formal verification, CLP, Primetime, PTPX, CECO... on area, timing, power and testability Minimum Qualifications – 2-6 years experience in Digital ASIC / Processor Design...

Company: Qualcomm
Posted Date: 20 Sep 2024

WLAN PHY Baseband(RTL) Digital Design Engineer

, Timing constraints, Python/Perl. Experience in design/debugging complex data-path/control-path IPs. Good communication...

Company: Qualcomm
Posted Date: 19 Sep 2024

Senior Engineer

analysis and Power optimization Knowledge on Formal verification is an added advantage Gate level Simulation with timing...

Posted Date: 18 Sep 2024

Senior Staff Engineer - Physical Design

of global Implementation team plays a key role in Netlist to GDS implementation, covering Synthesis, P&R, Timing, PV and Power...

Company: Marvell
Posted Date: 15 Sep 2024

Physical Design Engineer

on timing closure activities using tools like Tempus. - Ensure Design Rule Check (DRC) and Layout Versus Schematic (LVS...) closure. - Handle power and signal integrity analysis for critical designs. - Work on optimization techniques for timing...

Posted Date: 14 Sep 2024

IBM SENIOR LOGIC DESIGN ENGINEER – Core Execution(VSU) Unit

, Timing, FW, SW teams to develop the feature Signoff the Pre-silicon Design that meets all the functional, area and timing...

Company: IBM
Posted Date: 12 Sep 2024

IBM SENIOR LOGIC DESIGN ENGINEER – Core Units(Front End of Pipeline)

, Verification, DFT, Physical design, Timing, FW, SW teams to develop the feature Signoff the Pre-silicon Design that meets all the... functional, area and timing goals Participate in post silicon lab bring-up and validation of the hardware Lead a team...

Company: IBM
Posted Date: 12 Sep 2024

RTL Design Engineer- Sr Lead(Modem)

RTL needed to exercise the IP. You will be directly responsible for adapting the design for FPGA, come up with the timing... all aspects of FPGA design; constraint definition, synthesis, floor planning, P&R, Timing closure, bitfile generation...

Company: Qualcomm
Posted Date: 12 Sep 2024

Senior Engineer, Digital Design Engineer

, DFT concepts, power analysis Experience with developing timing constraints and ability to carry out logic synthesis... and Static timing analysis Good interpersonal, teamwork and communication skills to logically & effectively drive discussions...

Posted Date: 12 Sep 2024

IP Design Engineer (Bluetooth team)

and/or Python Skills RTL Design, Linting Tools, Synthesis, Timing Analysis, Low-Power Design Minimum Qualifications...

Company: Qualcomm
Posted Date: 12 Sep 2024

Semiconductor Package & System Planning Engineer

to product qualification. Experience with creating physical symbols, PCB routing and system timing. Work with team members...

Company: IBM
Posted Date: 06 Sep 2024

Design Engineer II

others: Demonstrate strong persuasion and timing skills. Remain open to be persuaded when appropriate. Inclusive work environment...

Company: BD
Posted Date: 04 Sep 2024

ASIC RTL Design - (Turing/AI ML) Sr Eng/Sr Lead/Staff Engineer

/workarounds. Work towards delivering with key design collaterals (timing constraints, UPF etc.). Desired Skillset: Good... Working with SOC DFT and PD teams as part of collaterals exchanges Knowledge of logic design principles along with timing...

Company: Qualcomm
Posted Date: 04 Sep 2024