Interconnect; System PLL IPs. Participate the SerDes architecture development with the DSP, Analog and Digital design teams... nodes, 5nm, 3nm and beyond. Design IP that includes but not limited to 112G/56G PAM4; 32G PAM2; DDR; Die-to-Die High Speed...
of experience or PhD in Electrical Engineering. Experience in high speed analog mixed signal design in 5nm and below for TSMC... provides leading-edge SerDes and Chiplet IO PHY solutions and other Analog Mixed-Signal IPs to support all Marvell products...