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Keywords: Senior Staff RTL/Integration Design Engineer, Location: Pune, Maharashtra

Page: 1

Senior Staff RTL/Integration Design Engineer

and similar time zones. The qualified candidate will be an expert in RTL design, best-in-class coding styles, algorithms..., and both Verilog and System Verilog. The qualified candidate will be expert in SoC integration and associated quality checks including...

Posted Date: 01 Jan 2025

Senior Staff RTL/Integration Design Engineer

and similar time zones. The qualified candidate will be an expert in RTL design, best-in-class coding styles, algorithms..., and both Verilog and System Verilog. The qualified candidate will be expert in SoC integration and associated quality checks including...

Posted Date: 01 Jan 2025