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Keywords: Senior E/E & Semiconductor Engineer - Design Verification Engineer, Location: San Francisco, CA

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Senior E/E & Semiconductor Engineer - Design Verification (DV) Engineer

Job description: Analog/Mixed-Signal Design Verification Key responsibilities: Extract modeling specifications... with layout engineer. This role will provide the ability to directly influence design related changes as required to meet...

Company: Capgemini
Location: San Francisco, CA
Posted Date: 19 Mar 2025

Senior E/E & Semiconductor Engineer - Design Verification (DV) Engineer

Job description: Analog/Mixed-Signal Design Verification Key responsibilities: Extract modeling specifications... with layout engineer. This role will provide the ability to directly influence design related changes as required to meet...

Company: Capgemini
Location: San Francisco, CA
Posted Date: 19 Mar 2025

Senior E/E & Semiconductor Engineer - CAD/EDA – Silicon Design/Verification Infrastructure Engineer

and environments to support ASIC design and verification processes. · Support Design Teams: Provide technical support to design teams... to ensure seamless operation and data flow. · Design Verification: Assist in the verification of ASIC designs, ensuring...

Company: Capgemini
Location: San Francisco, CA
Posted Date: 02 Feb 2025

Senior Digital (RTL) Design Engineer

Job Title: RTL Engineer Job Location: San Francisco CA Job Description We are seeking Digital Design/RTL Design... engineer for our Full Time Employment with Capgemini Engineering. Key Responsibilities: Perform detailed block design...

Company: Capgemini
Location: San Francisco, CA
Posted Date: 29 Jan 2025

Senior Analog Layout Engineer

Job description: Senior Analog Layout Engineer will be responsible for layout of high-performance analog cores... industry standard EDA tools from Cadence, Mentor and Synopsys for silicon chip design and production. · Must be able to set up...

Company: Capgemini
Location: San Francisco, CA
Posted Date: 18 Jan 2025