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Keywords: STA/Timing Engineer, Location: Bangalore, Karnataka

Page: 2

CPU Physical Design Engineer

Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical... Design and timing signoff for high speed cores. Should have good exposure to high frequency design convergence for physical...

Company: Qualcomm
Posted Date: 05 Dec 2024

Physical Design Engineer - Staff

in synthesis, place and route (PnR), and sign-off convergence, including Static Timing Analysis (STA) and sign-off optimizations... Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical...

Company: Qualcomm
Posted Date: 30 Nov 2024

IP Physical design engineer

Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical..., Formal verification, Physical Verification (DRC/LVS), Low Power verification, PDN, Timing Closure and / or power...

Company: Qualcomm
Posted Date: 28 Nov 2024

SOC Clock Lead - MTS Silicon Design Engineer

) and clock network optimization using tools like Synopsys FC, ICC2. Strong experience in static timing analysis (STA), clock..._ MTS SILICON DESIGN ENGINEER THE ROLE: The focus of this role is in developing clocking strategies that meet stringent...

Posted Date: 17 Nov 2024

Quantum Leap - Hardware Engineer -( Multiple Positions )

(perl, Python). STA Engineers: 2-15 years experience Experience with STA on large SOC with multi-scenario timing closure... and follow them through for completion. Experience in STA and timing closure of high-performance SOC designs in sub-micron...

Company: Qualcomm
Posted Date: 15 Nov 2024

DFT Engineer :: Design for testability, JTAG, Scan and BIST,ATPG :: 7+ Years

entire RTL 2 GDS Implementation flow including hierarchical floor planning, place & route, timing closure, power integrity..., static timing verification, physical verification and equivalence checks, with special focus on performance & die size...

Company: Cisco Systems
Posted Date: 13 Nov 2024

CPU Physical design engineer

Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical... and timing signoff for high speed cores. Should have good exposure to high frequency design convergence for physical design...

Company: Qualcomm
Posted Date: 13 Nov 2024

MSIP Digital Design Engineer

Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical...-plan development and debug. Develop timing constraints, deliver synthesized netlist to physical design team, and provide...

Company: Qualcomm
Posted Date: 10 Nov 2024

Lead Software Engineer

. Position: Lead Software Engineer Location: Bangalore Experience: 4-6 Years Job Description Cadence Design Systems... is looking for a highly motivated software engineer to work as a member of the R&D staff on Cadence’s Genus Synthesis Solution product. Genus...

Posted Date: 09 Nov 2024

IR/PDN Methodology Staff Engineer

Design automation engineer responsibilities would involve deploying new features/methodologies related to IR and IR-STA... Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical...

Company: Qualcomm
Posted Date: 22 Oct 2024

IR/PDN Methodology Engineer

engineer responsibilities would involve deploying new features/methodologies related to IR and IR-STA domain. Scope of the... Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical...

Company: Qualcomm
Posted Date: 22 Oct 2024

Lead Design Engineer

, which includes RTL development, RTL integration, maintain the timing constraint, Synthesis, Static timing analysis (STA), timing.... Knowledge of the IP/SoC level timing closure flow and methodology. Strong command of synthesis, STA, design for test...

Posted Date: 21 Dec 2024

Senior Lead Engineer - PD

and reaching Die file milestones Full chip and partition level timing analysis. Evaluate low power techniques and power reduction...-on experience on Netlist2GDSII Implementation i.e. Floorplanning, Power Grid Design, Placement, CTS, Routing, STA, Power Integrity...

Company: Quest Global
Posted Date: 16 Dec 2024

Senior Physical Design Engineer

and reaching Die file milestones Full chip and partition level timing analysis. Evaluate low power techniques and power reduction...-on experience on Netlist2GDSII Implementation i.e. Floorplanning, Power Grid Design, Placement, CTS, Routing, STA, Power Integrity...

Company: Quest Global
Posted Date: 16 Dec 2024

Lead Engineer - Physical Verification

, (congestion, timing) 4. Clock tree synthesis, in depth clock tree analysis. 5. Static timing analysis for block level, high... complex interface optimization knowledge. 6. Expertise in high-speed timing blocks. 7. Expertise in lower tech nodes. 8...

Company: Quest Global
Posted Date: 16 Dec 2024

Senior Engineer - PD

block and sub system level Place and Route  Work closely with the STA and PV teams to close timing and sign off checks...

Company: Quest Global
Posted Date: 16 Dec 2024

PD Lead Engineer

Full chip and partition level timing analysis. Evaluate low power techniques and power reduction opportunities Perform... on Netlist2GDSII Implementation i.e. Floorplanning, Power Grid Design, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical...

Company: Quest Global
Posted Date: 16 Dec 2024

Senior Physical Design Engineer

ICC2/Synopsys and Innovus/Cadence flows preferred. Well versed with timing constraints, STA and timing closure. Good... plans, abstract view generation, RC extraction, PNR, STA, EM,IR DROP, DRCs & schematic to layout verification. Work...

Company: Nvidia
Posted Date: 03 Dec 2024

Senior Staff Engineer, DFT

/Physical design/STA/ATE teams as needed. What We're Looking For Bachelor’s/Master's degree in Computer Science, Electrical... is looking for will have: Very good knowledge on SCAN/ATPG/JTAG/MBIST Proven experience on gate level simulations with no-timing and SDF based...

Company: Marvell
Posted Date: 22 Nov 2024

Senior Staff DFT Engineer

will have to be proficient in the area of DFT/DFX implementation, Verification , pattern generation/simulation, Timing, Post-Silicon Debug..., Synthesis, DFT and STA Strong fundamentals in Digital Circuit Design is required Prior experience in ASIC design...

Company: Marvell
Posted Date: 19 Nov 2024