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Keywords: RTL Verification Engineer, Location: Bangalore, Karnataka

Page: 4

Sr. Silicon Design Engineer

_ SENIOR SILICON DESIGN ENGINEER THE ROLE: We are looking for an adaptive, self-motivative design engineer... with architects, Verification engineers, and Physical design Engineers to understand the new features to be designed and integrated...

Posted Date: 21 Nov 2024

Digital Design Engineer

Engineer Job Responsibilities: Design key digital blocks such as accelerators/ datapath IP in Verilog/ System Verilog... for seamless integration into design flow at different stages – RTL/ constraints/ CDC waivers, timing wavers, DFT DRCs and waivers...

Posted Date: 19 Nov 2024

Quantum Leap - Hardware Engineer -( Multiple Positions )

. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits... solutions and meet performance requirements. We have multiple roles in all Hardware disciplines. RTL Design Engineers: 2-15...

Company: Qualcomm
Posted Date: 15 Nov 2024

Senior Staff Digital IC Design Engineer

Responsibilities: MaxLinear is seeking a Senior Staff ASIC Design Engineer to join our Digital ASIC Design group... understanding of digital communication systems, digital design fundamentals and knowledge of CMOS logic fundamentals. Engineer...

Company: MaxLinear
Posted Date: 15 Nov 2024

SMTS Silicon Design Engineer

_ SMTS SILICON DESIGN VERIFICATION ENGINEER The Role The AMD IOHUB Team (part of the NBIO organization...) is looking for an ASIC Design Verification Engineer to join our growing team. We develop leading-edge I/O connectivity and virtualization...

Posted Date: 14 Nov 2024

DFT Engineer :: Design for testability, JTAG, Scan and BIST,ATPG :: 7+ Years

entire RTL 2 GDS Implementation flow including hierarchical floor planning, place & route, timing closure, power integrity..., static timing verification, physical verification and equivalence checks, with special focus on performance & die size...

Company: Cisco Systems
Posted Date: 13 Nov 2024

STA Engineer | Static Timing Analysis & ECO generation | Synopsys PrimeTime, Tweaker, Prime Closure :: 7+ Years

entire RTL 2 GDS Implementation flow including hierarchical floor planning, place & route, timing closure, power integrity..., static timing verification, physical verification and equivalence checks, with special focus on performance & die size...

Company: Cisco Systems
Posted Date: 13 Nov 2024

CPU Physical design engineer

Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical.... Work independently in the areas of RTL to GDSII implementation. Ability to collaborate and resolve issues wrt constraints...

Company: Qualcomm
Posted Date: 13 Nov 2024

MSIP Digital Design Engineer

Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical.... General Summary: Front-End implementation of MSIP (Temp/Voltage/Security Sensors, Controllers) designs RTL development...

Company: Qualcomm
Posted Date: 10 Nov 2024

Lead Software Engineer

, verification, RTL compilation, placement, power analysis, routing, extraction, and optimization. You will be part of a team.... Position: Lead Software Engineer Location: Bangalore Experience: 4-6 Years Job Description Cadence Design Systems...

Posted Date: 10 Nov 2024

Staff Digital Engineer

. Requisition ID: 74460 Job Description Summary: Digital design engineer developing complex mixed-signal ICs for frequency... in digital system architecture, block- and system-level RTL design/coding, algorithm and firmware development, digital circuit...

Company: Skyworks
Posted Date: 04 Nov 2024

CPU/IP SDE/MTS/SMTS Silicon Design Engineer

_ CPU/IP Verification SDE/MTS/SMTS SILICON DESIGN ENGINEER THE ROLE: The person will be part of AMD's CPU verification... pipeline stages to various complex features and structures, debugging functional issues of RTL and verification components...

Posted Date: 26 Oct 2024

DFT Engineer

_ SENIOR SILICON DESIGN ENGINEER - DFT THE ROLE: As a Senior Silicon Design Engineer, you will work with DFT experts... and Mentors for DFT Activities such as SCAN, ATPG,MBIST and DFT RTL Integration etc. THE PERSON: You have a passion for modern...

Posted Date: 26 Oct 2024

ASIC Engineer, Emulation

development. Develop emulation tools, workflows and infrastructure in collaboration with RTL, verification, validation and SW... Engineer, Emulation Responsibilities Develop emulation testbenches in System Verilog and/or C/C++. Deliver emulation...

Company: Meta
Posted Date: 25 Oct 2024

ASIC Engineer, Emulation

development. Develop emulation tools, workflows and infrastructure in collaboration with RTL, verification, validation and SW... Engineer, Emulation Responsibilities Develop emulation testbenches in System Verilog and/or C/C++. Deliver emulation...

Company: Meta
Posted Date: 25 Oct 2024

CPU Physical Design - MTS Silicon Design Engineer

_ SDE/MTS SILICON DESIGN ENGINEER THE ROLE: The position will involve working with a very experienced CPU physical...-edge technology. THE PERSON: Engineer with a good attitude, strong analytical skills, effective communication...

Posted Date: 20 Oct 2024

Sr. Silicon Design Engineer

_ SENIOR SILICON DESIGN ENGINEER KEY RESPONSIBILITIES: This position is for a physical design engineer in AMD’s Radeon..., FC level Clock Routing, Bump Routing, RDL layer Routing, Physical Verification, Signoff checks. Understanding...

Posted Date: 20 Oct 2024

ASIC Engineer Design

and IP for data center applications. ASIC Engineer Design Responsibilities Architecture exploration Micro-architecture... development RTL development using Verilog, System Verilog and HLS Lint, CDC, Synthesis, & Power Optimization Soft and hard...

Company: Meta
Posted Date: 18 Oct 2024

Graphics Performance Modelling Engineer - Staff/ Senior Staff

and maintain tests for pre-silicon and post-silicon power verifications. Work closely with multiple teams such as RTL designer..., architecture, design verification, compiler, driver, silicon implementation, and post-silicon teams Knowledge of Graphics...

Company: Qualcomm
Posted Date: 28 Dec 2024

Lead Design Engineer

closure, power optimization, and physical verification for both of block and Chip top level You will mainly work on PHY RTL..., which includes RTL development, RTL integration, maintain the timing constraint, Synthesis, Static timing analysis (STA), timing...

Posted Date: 22 Dec 2024