specification documents. Writing RTL (mainly Verilog or System Verilog), run block-level simulation, FPGA backend or ASIC synthesis... design field Strong RTL coding skills Strong scripting skills Familiar with SONET, OTN, Ethernet, PCIe Excellent...
requirements, RTL design, verification, synthesis, static timing analysis. Enhance design methodology and workflow for greater... efficiency. Design RTL for various SerDes IPs with data rates from 10Gbps to 224Gbps for diverse applications. Collaborate...
. Experience with automated RTL code generation from high-level system design languages such as CatapultC (HLS). Programming...
RTL (mainly Verilog or System Verilog), run block-level simulation, FPGA backend or ASIC synthesis, DFT insertion, timing... and support team. Requirements A minimum of 8 years of relevant experience in the ASIC/FPGA design field Strong RTL coding...
Expect As ASIC Timing Engineer you will be responsible for post RTL design flow. You will be responsible for block... of experience. Solid post-RTL experience, including synthesis, timing analysis, and physical design. Ability to perform custom...
, or write appropriate test plans Design RTL code in verilog and/or verification environments and test cases in UVM Assist... with RTL lint, block level assertions, code coverage closure, CDC, synthesis and timing closure. Able to debug complex design...
. Partnering with rtl circuit designers and other layout engineers, you will create adequate floorplan, design power grid and clock... of quick PnR to refine the design and correlation. In working with the RTL designers and architects to understand the circuit...
path RTL implementation using Verilog, synthesis and backend resources Integrate vendor IP and support Well versed... and implement digital features of a chip. Participate in various aspects of chip design RTL development, synthesis, static timing...