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Keywords: RTL, Location: California

Page: 5

Graphics FE Integration Engineer

. As a member of GPU FE Design integration team, you will create GPU RTL by integrating various IPs following architectural..., you will be responsible for: - RTL integration, assembly, partitioning, transformation and analysis. - Package, qualify and deliver FE design...

Company: Apple
Location: Santa Clara, CA
Posted Date: 16 Jan 2025

Graphics FE Integration Engineer

. As a member of GPU FE Design integration team, you will create GPU RTL by integrating various IPs following architectural..., you will be responsible for: - RTL integration, partitioning, design analysis and qualification. - Run logic equivalence checking...

Company: Apple
Location: Santa Clara, CA
Posted Date: 16 Jan 2025
Salary: $121900 - 183600 per year

Design Verification Engineer

/ASIC/SoC design or implementation(such as RTL coding, simulation/verification, Synthesis, floor planning, physical design... technologies as part of IP/ASIC/SoC design or implementation. Experience with RTL coding, simulation/verification, synthesis...

Company: Prodapt
Location: San Jose, CA
Posted Date: 16 Jan 2025

Wireless MAC Design Engineer

vertically coordinated engineering team spanning Systems/PHY/MAC architecture and design, digital RTL design and integration, RF.... Description Description - You will prepare microarchitecture and RTL for digital logic of the wireless MAC based on a set of functional requirements...

Company: Apple
Location: Sunnyvale, CA
Posted Date: 16 Jan 2025

ASIC Design Engineer - Cisco Silicon One

on RTL Design Create micro-architecture specifications and participate in reviews Implement Verilog RTL to meet timing...

Company: Cisco Systems
Location: San Jose, CA
Posted Date: 15 Jan 2025
Salary: $133300 - 186800 per year

Design Verification Engineer

as part of IP/ASIC/SoC design or implementation(such as RTL coding, simulation/verification, Synthesis, floor planning.../SerDes/PCIe technologies as part of IP/ASIC/SoC design or implementation. Experience with RTL coding, simulation...

Company: Prodapt
Location: San Jose, CA
Posted Date: 15 Jan 2025

Senior ASIC Design Engineer

. Your Impact Author design specifications and participate in micro-architecture specification reviews. Implement Verilog RTL... with RTL modification. Preferred Qualifications Master's degree in Electrical or Computer engineering and 4+ years...

Company: Cisco Systems
Location: San Jose, CA
Posted Date: 15 Jan 2025

Staff ASIC Design Engineer

understanding of physical design Proficient in Verilog and System Verilog for RTL design and verification. Experience with ASIC...

Company: Western Digital
Location: Roseville, CA
Posted Date: 15 Jan 2025

Senior Staff Emulation Engineer - ZEBU

design center (ODC) or staff augmentation. Services offered by Prodapt ASIC BU: SoC/ASIC RTL Design, UVM based verification.../block-level test benches, executing verification plans, analysis/debugging RTL, and gate-level emulation failures...

Company: Prodapt
Location: San Jose, CA
Posted Date: 15 Jan 2025

Formal Verification Intern - Summer 2025

with sufficient coverage. Drive tools to realize their best performance. Debug RTL to identify causes of failure scenarios...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 15 Jan 2025

Power UPF Methodology Engineer

methods. Familiar with entire RTL2GDS flow (RTL sim (VCS), equivalence, synthesis, P&R, intent checking...

Company: Apple
Location: Cupertino, CA
Posted Date: 15 Jan 2025

Director SoC Architecture

design and development RTL) · Experience with chiplet architecture and partitioning for SiP packages. · Experience...

Company: Capgemini
Location: San Francisco, CA
Posted Date: 15 Jan 2025

Sr./Staff ASIC Design Engineer

Participate in both top level and module level RTL coding, simulation, synthesis and timing closure Generate test...

Company: OmniVision
Location: Santa Clara, CA
Posted Date: 15 Jan 2025
Salary: $130000 - 200000 per year

Senior Circuit Design Engineer - Power Modeling and Simulation

, mixed-signal RTL+spice, s-parameters, etc. Familiarity/experience with industry -standard design and EDA tools (Cadence...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 15 Jan 2025

SoC Chiplet Design Lead

to balance trade-offs in performance, power, cost, and features. Lead efforts in RTL design, design-for-test (DFT) strategies... from concept to high-volume production. Expertise in RTL design using Verilog or SystemVerilog. In-depth knowledge of SoC...

Company: SkillTorch
Location: Santa Clara, CA
Posted Date: 15 Jan 2025

Senior Physical Design Engineer

augmentation. Services offered by Prodapt ASIC BU: SoC/ASIC RTL Design, UVM based verification, Emulation, FPGA based validation...

Company: Prodapt
Location: San Jose, CA
Posted Date: 15 Jan 2025

Sr. Physical Design Engineer

augmentation. Services offered by Prodapt ASIC BU: SoC/ASIC RTL Design, UVM based verification, Emulation, FPGA based validation...

Company: Prodapt
Location: San Jose, CA
Posted Date: 15 Jan 2025

Senior Staff Emulation Engineer - ZEBU

design center (ODC) or staff augmentation. Services offered by Prodapt ASIC BU: SoC/ASIC RTL Design, UVM based verification.../block-level test benches, executing verification plans, analysis/debugging RTL, and gate-level emulation failures...

Company: Prodapt
Location: San Jose, CA
Posted Date: 14 Jan 2025

ASIC Timing Engineer, Staff

signal), timing constraints and provide solutions if required. Good understanding of RTL to GDS digital flow. Knowledge of DC...

Company: Qualcomm
Location: San Diego, CA
Posted Date: 14 Jan 2025

Senior ASIC Technical Lead

-architecture specifications. Implement Verilog RTL to meet timing and performance requirements. Help define, evolve, and support...

Company: Cisco Systems
Location: San Jose, CA
Posted Date: 14 Jan 2025