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Keywords: RTL, Location: California

Page: 19

RF Systems Engineer

/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design...

Company: Apple
Location: San Diego, CA
Posted Date: 24 Oct 2024

Physical Design Lead - Custom Silicon Management

a number of complex chips - from gates to GDS. Working knowledge of front-end design methodology including basic RTL coding, synthesis...

Company: Apple
Location: Cupertino, CA
Posted Date: 24 Oct 2024

RFIC Layout Engineer

/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design...

Company: Apple
Location: Irvine, CA
Posted Date: 24 Oct 2024

Digital Circuit Design Intern

to learn and adapt to new concepts Additional Desirable Skills: Having experiences with Verilog RTL coding design. EEO...

Company: MACOM
Location: Newport Beach, CA
Posted Date: 24 Oct 2024

Staff ASIC Design Engineer - Functional Safety

, and ensuring the design meets Automotive Safety Integrity Levels (ASIL). Analyze RTL designs including third-party IP tools...+ years of RTL design experience using SystemVerilog. In-depth knowledge of ISO-26262 as it relates to ASIC design. In-depth...

Company: Aeva
Location: Mountain View, CA
Posted Date: 24 Oct 2024
Salary: $181300 - 245300 per year

Senior DFT Engineer

on Design-for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture... experience with hardware design specifications and verification plan/matrix, RTL & testbench implementations. Prior experience...

Company: Cisco Systems
Location: San Jose, CA
Posted Date: 23 Oct 2024

Mixed-Signal IP Firmware Engineer

. You will be required to understand how these IPs work by reading their specifications and RTL implementations. You will also occasionally write RTL... understanding of computer architecture. Solid understanding of ARM AHB/APB protocols. Deep knowledge of RTL design. Deep...

Company: Apple
Location: Cupertino, CA
Posted Date: 23 Oct 2024
Salary: $121900 - 183600 per year

Design Verification Engineer

stimulus and checkers, test-writing, debug, coverage, sign-off for RTL freeze and tape-out...

Company: Apple
Location: Cupertino, CA
Posted Date: 23 Oct 2024

ASIC Engineer, Physical Design

performance and power. Work with the RTL design team to understand partition architecture and drive physical aspects early... in the design cycle. Interface with the RTL design team to drive design modifications to resolve congestion/timing issues...

Company: Meta
Posted Date: 23 Oct 2024

Principal Power Analysis Engineer

development cycle from early modeling, RTL analysis, to in-depth timing annotated netlist analysis. Collaborate with post-silicon... strong technical leadership, with ability to develop accurate project plans involving multiple teams. Expertise in RTL and Netlist...

Posted Date: 23 Oct 2024

Design Verification Engineer

stimulus and checkers, test-writing, debug, coverage, sign-off for RTL freeze and tape-out...

Company: Apple
Location: San Diego, CA
Posted Date: 23 Oct 2024

Hardware Engineering Failure Analysis (Onsite)

, not RTL or coding. that's not required. Does not need to have networking background....

Company: SEDAA
Location: San Jose, CA
Posted Date: 23 Oct 2024

Physical Design Engineer

Jose, CA with a primary focus on Design-for-Test. You will work with Front-end RTL teams, backend physical design teams... implementation from RTL to GDSII. As Physical Verification Engineer your main responsibilities will include: Perform full chip DRC...

Company: Cisco Systems
Location: San Jose, CA
Posted Date: 22 Oct 2024