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Keywords: RTL, Location: California

Page: 16

RFIC Design Engineer

spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation...

Company: Apple
Location: Cupertino, CA
Posted Date: 01 Nov 2024

RFIC Design Engineer

spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation...

Company: Apple
Location: Irvine, CA
Posted Date: 01 Nov 2024

ASIC/SoC Design Verification Engineer

or DSP core.Experience in verifying designs at both of RTL level and post-P&R gate level. 3. Ability to work in a startup...

Company: IntelliPro Group
Location: Fremont, CA
Posted Date: 01 Nov 2024

ASIC Engineering Technical Leader

with primary focus on RTL Design. Create micro-architecture specifications and participate in reviews Implement Verilog RTL.... Perform diagnostic and post silicon validation tests in the lab. Who You'll Work With You will work with front-end RTL...

Company: Cisco Systems
Location: San Jose, CA
Posted Date: 31 Oct 2024

FE Design and Timing Analysis Engineer

spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation... wireless SoCs from RTL to delivery of our final GDSII. Your responsibilities include, but are not limited to: • Generate chip...

Company: Apple
Location: Sunnyvale, CA
Posted Date: 31 Oct 2024

RFIC - PLL Design Engineer

integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC, VLSI/RTL design and integration...

Company: Apple
Location: Sunnyvale, CA
Posted Date: 31 Oct 2024

RFIC - PLL Design Engineer

integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC, VLSI/RTL design and integration...

Company: Apple
Location: Irvine, CA
Posted Date: 31 Oct 2024

PLL/Clocking Design Engineer

performance and impact on loop dynamics. Ability to design/debug RTL is a plus. Attention to Detail: Exceptional focus...

Company: Apple
Location: San Diego, CA
Posted Date: 31 Oct 2024

RFIC Layout Engineer

and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering...

Company: Apple
Location: San Diego, CA
Posted Date: 31 Oct 2024

RFIC - PLL Design Engineer

integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC, VLSI/RTL design and integration...

Company: Apple
Location: San Diego, CA
Posted Date: 31 Oct 2024

Wireless SoC RF Integration and Validation Engineer

spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation...

Company: Apple
Location: San Diego, CA
Posted Date: 31 Oct 2024

FE Design and Timing Analysis Integration Engineer

spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation... wireless SoCs from RTL to delivery of our final GDSII. Your responsibilities include, but are not limited to: • Generate chip...

Company: Apple
Location: Sunnyvale, CA
Posted Date: 31 Oct 2024

SRAM Circuit Design Engineer

team to create optimal GDS. - Verify extracted GDS meets design specifications. - Backend verification, IR/EM - Write RTL... design/architecture, memory hierarchy is a huge plus. Working knowledge of RTL modeling. Solid understanding of industry...

Company: Apple
Location: Santa Clara, CA
Posted Date: 31 Oct 2024

ASIC/SoC Design Verification Engineer——An In-memory computing edge AI Company

in verifying designs at both of RTL level and post-P&R gate level. Ability to work in a startup environment, and to work...

Company: IntelliPro Group
Location: Fremont, CA
Posted Date: 31 Oct 2024

Eng Sr Prin - Elec

activities including assisting in requirements generation and design architecture, ownership of RTL coding, synthesis, place...

Company: BAE Systems
Location: San Diego, CA
Posted Date: 31 Oct 2024

RFIC Layout Engineer

and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering...

Company: Apple
Location: Irvine, CA
Posted Date: 31 Oct 2024

PLL/Clocking Design Engineer

performance and impact on loop dynamics. Ability to design/debug RTL is a plus. Attention to Detail: Exceptional focus...

Company: Apple
Location: Cupertino, CA
Posted Date: 31 Oct 2024

PLL/Clocking Design Engineer

performance and impact on loop dynamics. Ability to design/debug RTL is a plus. Attention to Detail: Exceptional focus...

Company: Apple
Location: Cupertino, CA
Posted Date: 31 Oct 2024

Wireless SoC RF Integration and Validation Engineer

spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation...

Company: Apple
Location: Irvine, CA
Posted Date: 31 Oct 2024

RFIC - PLL Design Engineer

integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC, VLSI/RTL design and integration...

Company: Apple
Location: Sunnyvale, CA
Posted Date: 31 Oct 2024