• Working with RTL and DV teams to recommend System Verilog assertions needed to support CDC/RDC/STA constraints and assumptions... • Highlighting to the RTL team any CDC/RDC issues and recommending solutions to them and educating them on CDC/RDC issues and the...
to model performance and power. Build power estimation flows at various levels of abstraction: C-model, RTL, Gate, Layout... between performance and power. Post-silicon bring-up, debug and identify issues on emulator and RTL. Understanding of ASIC design...
: Strong understanding of the complete IC design flow, from front-end design (RTL, synthesis, simulation) to back-end physical implementation...
and 20+ years of relevant industry experience. We seek individuals with expert design experience to understand RTL design... analysis and optimizations using advanced synthesis techniques and RTL design improvement for optimal area, timing and power...
Familiarity with ASIC design process including RTL, synthesis, logic equivalence, DFT, and backend related methodology and tools...
of high performance SoC design at both the block and subchip levels, as well as the full-chip level from RTL to GDSII... from RTL to GDSII. Good knowledge of EM-IR sign-off requirements. Experience in using EDA tools like Synopsys (/Cadence...
. Prior experience in managing both software and ASIC design flow (architecture, micro-architecture, RTL, Synthesis...
team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration..., you will be responsible for pre-silicon RTL verification of block and top-level SOC. With deep understanding of SOC architecture...
team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration..., you will be responsible for pre-silicon RTL verification of block and top-level SOC. With deep understanding of SOC architecture...
stimulus and checkers, test-writing, debug, coverage, sign-off for RTL freeze and tape-out...
and participate in micro-architecture specification reviews. Implement Verilog RTL to meet timing and performance requirements. Help... with RTL modification. Experience developing micro-architecture solutions and RTL implementation. Preferred Qualifications...
and participate in micro-architecture specification reviews. Implement Verilog RTL to meet timing and performance requirements. Help.... Interactive and waveform debug experience. Experience resolving setup and hold timing violations with RTL modification...
. As a member of GPU FE Design integration team, you will create GPU RTL by integrating various IPs following architectural..., you will be responsible for: - RTL integration, assembly, partitioning, transformation and analysis. - Package, qualify and deliver FE design...
. As a member of GPU FE Design integration team, you will create GPU RTL by integrating various IPs following architectural..., you will be responsible for: - RTL integration, partitioning, design analysis and qualification. - Run logic equivalence checking...
. As a member of GPU FE Design integration team, you will create GPU RTL by integrating various IPs following architectural..., you will be responsible for: - RTL integration, partitioning, design analysis, qualification, packaging and delivery. - Run logic equivalence...
vertically coordinated engineering team spanning Systems/PHY/MAC architecture and design, digital RTL design and integration, RF.... Description Description - You will prepare microarchitecture and RTL for digital logic of the wireless MAC based on a set of functional requirements...
manager to define block micro-architecture and write design specification. Implement a specification using RTL coding... with focus on front-end complex RTL design Programming skills in Verilog Must be familiar with all stages of the ASIC design...
, mixed-signal RTL+spice, s-parameters, etc. Familiarity/experience with industry -standard design and EDA tools (Cadence...
Participate in both top level and module level RTL coding, simulation, synthesis and timing closure Generate test...
to balance trade-offs in performance, power, cost, and features. Lead efforts in RTL design, design-for-test (DFT) strategies... from concept to high-volume production. Expertise in RTL design using Verilog or SystemVerilog. In-depth knowledge of SoC...