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Keywords: RTL, Location: California

Page: 12

ASIC Verification Engineer

developed in the industry. You will work with front-end RTL Design and Verification teams and Architects to understand chip...

Company: Cisco Systems
Location: San Jose, CA
Posted Date: 24 Nov 2024
Salary: $133300 - 186800 per year

Modem Systems Engineer - 5G/6G

. - Implement system models and perform detailed performance investigations to allow performance sign-off and enable RTL development...

Company: Apple
Location: Sunnyvale, CA
Posted Date: 24 Nov 2024

Hardware Systems Engineer - Board Design

and transmission lines, timing analysis, digital logic RTL experience using Verilog or VHDL. Preferably FPGA design experience...

Company: Apple
Location: Cupertino, CA
Posted Date: 24 Nov 2024

UVM/SystemVerilog Design Verification Engineer

Job Description: As an FPGA design engineer, you will take ownership of project components and develop scalable RTL...: RTL Coding, Synthesis, Timing Closure, and Bitfile Generation: Develop efficient microarchitecture and RTL code using...

Location: Goleta, CA
Posted Date: 24 Nov 2024

Circuits Physical Design Engineer

through RTL to GDS steps. This will include physical synthesis, placement, CTS, routing, timing optimization, leakage recovery...

Company: Apple
Location: Santa Clara, CA
Posted Date: 23 Nov 2024

Design Engineer Architect/Lead

customer on aspects including but limited to physical synthesis, influencing RTL content and coding styles that will lend...

Company: Broadcom
Location: San Jose, CA
Posted Date: 23 Nov 2024

RFIC Layout Designer

and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering...

Company: Apple
Location: San Diego, CA
Posted Date: 23 Nov 2024
Salary: $36.55 - 62.6 per hour

GPU Formal Verification Engineer

equivalence scenarios such as clock gating, and verifying datapath equivalence of C and RTL models. You will diagnose formal... failures and work closely with RTL designers to update formal constraints or RTL code in order to fix the failures. Skills...

Company: 삼성전자
Location: San Jose, CA
Posted Date: 22 Nov 2024

Principal Digital IC Design Engineer

. Qualifications You Must Have: Experience with full digital design flow that includes writing RTL using Verilog & SystemVerilog..., constructing testbenches to perform RTL simulation & verification, performing Synthesis, Static Timing Analysis, Place-and-Route...

Location: California
Posted Date: 22 Nov 2024
Salary: $96000 - 200000 per year

Circuits Physical Design Engineer

through RTL to GDS steps. This will include physical synthesis, placement, CTS, routing, timing optimization, leakage recovery...

Company: Apple
Location: San Diego, CA
Posted Date: 22 Nov 2024

ASIC DFT Verification Technical Leader

Jose, CA with a primary focus on Design-for-Test. You will work with Front-end RTL teams, backend physical design teams... specifications and verification plan/matrix, RTL & testbench implementations. Prior experience on DFT quality sign off checklist...

Company: Cisco Systems
Location: San Jose, CA
Posted Date: 21 Nov 2024

Principal Engineer ASIC

based on requirements Development of RTL Design for digital systems Perform simulation and emulation (lab integration... hardware is highly desired - Experience with RTL design using Xilinx Vivado or Microchip Libero - Experience...

Posted Date: 20 Nov 2024
Salary: $121400 - 182000 per year

Sr. Principal Engineer ASIC

based on requirements Development of RTL Design for digital systems Perform simulation and emulation (lab integration...; or a STEM Master's degree with 6+ years of experience; or a STEM PhD. degree with 4+ years of experience - Experienced in RTL...

Posted Date: 20 Nov 2024

ASIC Design for Test - Technical Lead

Implementation Technical Lead with a primary focus on Design-for-Test. You will work with Front-end RTL teams, backend physical... in the RTL. Work closely with the design/design-verification and PD teams to enable the integration and validation of the...

Company: Cisco Systems
Location: San Diego, CA
Posted Date: 20 Nov 2024

ASIC Design Engineer

Experience in SoC front-end ASIC RTL digital logic design using Verilog or System Verilog. Hands on experience in all aspects...

Company: Apple
Location: Cupertino, CA
Posted Date: 20 Nov 2024

Lead NoC Performance Architect

range of SoCs spanning multiple product streams, correlate models against RTL behavior, prototype ideas and help productize... unit-tests and debugging mismatches against expectations Work with architects and RTL developers to productize the...

Company: Qualcomm
Location: Santa Clara, CA
Posted Date: 20 Nov 2024

SoC Design and Integration Engineer - Sr Eng

player with good communication skill. This is a great opportunity to join a fast-paced SoC team responsible for RTL Design...

Company: Qualcomm
Location: San Diego, CA
Posted Date: 18 Nov 2024
Salary: $115600 - 173400 per year

Low Power ASIC Engineer (Next-Gen, High-Speed Memory Subsystem)

of next Generation, high performance, low power Memory Subsystem RTL Design, flows and methodology for high performance ASICs in sub-4nm... designs. Strong knowledge in the entire low power, high performance ASIC/SoC design flows (micro-architecture, RTL design...

Company: Qualcomm
Location: San Diego, CA
Posted Date: 17 Nov 2024

FPGA Firmware Engineer / FPGA Design Engineer

-on experience with System Verilog, RTL/HDL, FPGA (Xilinx Ultrascale, Ultrascale+, MPSoC, Intel Stratix) and FPGA Tools (Xilinx...

Company: Qualcomm
Location: San Diego, CA
Posted Date: 17 Nov 2024
Salary: $115600 - 173400 per year

Senior Resiliency and Safety Architect

to enable, run, and debug tests on Architecture models. Support test debug on RTL, emulation, and silicon. Run simulations... (e.g., transient faults, stuck-at faults) in both RTL and gate-level netlists. Collaborate with safety engineering teams...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 17 Nov 2024