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Keywords: RTL, Location: California

Page: 12

FPGA Circuit Design Engineer

chip, IP fabrics and interconnects, RTL design, and verification teams to develop new capabilities around FPGA solutions...

Company: Altera
Location: San Jose, CA
Posted Date: 26 Feb 2026

Physical Design Engineer

role in the backend implementation flow — from RTL/netlist through GDSII/tape-out for FPGA/SoC devices..., signal/power integrity reporting, and corrective action planning. Interfacing with front-end teams (RTL, architecture), CAD...

Company: Altera
Location: San Jose, CA
Posted Date: 26 Feb 2026
Salary: $113700 - 164700 per year

ASIC Verification/Design Engineering Intern

senior members of the ASIC / VLSI team. Responsibilities may include RTL/Physical Design, Pre- Silicon verification; Post...

Posted Date: 26 Feb 2026

Senor SoC Design Engineer

will include working on Intellectual Property (IP) microarchitecture specification, Register Transfer Level (RTL) design, System.... 8+ years expertise in Digital Design including microarchitecture specification development, RTL coding in Verilog/System...

Company: Microsoft
Location: Mountain View, CA
Posted Date: 26 Feb 2026

Senior ASIC Methodology Engineer - LPU Division

record developing groundbreaking ASIC design frameworks and flows. First-hand experience with RTL, functional verification...

Company: Nvidia
Location: California
Posted Date: 26 Feb 2026

R&D Engineering, Sr Staff

to define and implement partitioning methodologies that improve system performance and scalability. Analyzing complex RTL... in hardware partitioning, emulation, or hardware-assisted verification. Strong proficiency in RTL design (Verilog, SystemVerilog...

Company: Synopsys
Location: Sunnyvale, CA
Posted Date: 26 Feb 2026

West Area Channel FAE

and digital logic design 3+ years of experience in Field Applications Engineering Proficient in RTL (Verilog/VHDL), timing...

Company: Altera
Location: San Jose, CA
Posted Date: 26 Feb 2026

Design Verification Engineer

and communicates with Architects, micro architects, full chip architects, RTL developers, post silicon, and physical design teams...

Company: Altera
Location: San Jose, CA
Posted Date: 26 Feb 2026
Salary: $113700 - 164700 per year

Engineer 3 - Electrical Engineering

for advanced robotic and medical systems. The engineer will own RTL design from architecture through validation, working hands..., but are not limited to: Designing, developing, optimizing, and maintaining FPGA RTL using Verilog/SystemVerilog and/or VHDL. Supporting...

Company: Ampcus
Location: Santa Clara, CA
Posted Date: 26 Feb 2026

Senior Design Engineer

Bench to perform sub-system and full chip Verilog verification using UVM Perform RTL Code coverage and review Functional...

Company: Micron
Location: San Jose, CA
Posted Date: 26 Feb 2026

ASIC Intern

senior members of the ASIC / VLSI team. Responsibilities may include RTL/Physical Design, Pre-Silicon verification; Post...

Posted Date: 26 Feb 2026

Digital IC Design Engineer

-Number based modeling and verification is a must 5+ years of experience in RTL based digital design capture and verification... in fabricated silicon products is required Experience with RTL-to-GDS digital design implementation using industry standard tools...

Company: Protocol Labs
Location: Alameda, CA
Posted Date: 26 Feb 2026

FPGA Circuit Design Engineer

industry. Experience in digital circuit design at the transistor and block level and in generation of schematics from RTL...

Company: Altera
Location: San Jose, CA
Posted Date: 26 Feb 2026
Salary: $127400 - 184000 per year

FPGA/Firmware Engineer

development, from RTL design to embedded firmware and who thrive in high-ownership, cross-disciplinary environments. The position..., from concept to deployment Optimize RTL designs for logic resource utilization, power efficiency, and reliable timing closure...

Company: Protocol Labs
Location: Alameda, CA
Posted Date: 26 Feb 2026
Salary: $150000 - 200000 per year

Timing Engineer (Sr. Staff Engineer)

and validate timing ECOs, partnering with physical design and RTL teams for quick closure. Global clock planning for easier...

Company: Altera
Location: San Jose, CA
Posted Date: 26 Feb 2026
Salary: $127400 - 184400 per year

Product Development Engineer

insertion, BIST (Built-In Self-Test), and test compression techniques. Collaborate with RTL design and verification teams..., Tessent Shell etc). Experience with RTL design, synthesis, and verification flows. Experience with fault grading, test...

Company: Altera
Location: San Jose, CA
Posted Date: 26 Feb 2026
Salary: $113700 - 164700 per year

Senior DFT Design Engineer

at both RTL and gate level. Experience in EDA tools such as synthesis and scan insertion tools, ATPG tools, simulation and debug...

Company: Altera
Location: San Jose, CA
Posted Date: 26 Feb 2026

DSP Design Engineer

parameterizable and efficient IP implementations. Will determine microarchitecture design, logic design, RTL coding, and system... for next-generation FPGAs Contribute to all phases of the design lifecycle including specification development, RTL design, timing...

Company: Altera
Location: San Jose, CA
Posted Date: 26 Feb 2026

Senior Design Automation Engineer - Front End Design Verification

is responsible for building and maintaining the core automation infrastructure that supports Altera’s FPGA design flows—from RTL... field with 8+ years of relevant industry experience, including: Hands-on experience with Front End RTL and or Design...

Company: Altera
Location: San Jose, CA
Posted Date: 26 Feb 2026

Design Verification Lead

with architects and RTL designers to assess the impact of architectural changes. Create, develop, and maintain UVM/SystemVerilog...

Company: Capgemini
Location: Santa Clara, CA
Posted Date: 26 Feb 2026
Salary: $86900 - 203800 per year