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Keywords: Principal Engineer, ASIC Development Engineering ( CAD / PDK / PCELL / LVS ) 7+ Years, Location: Bangalore, Karnataka

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Principal Engineer, ASIC Development Engineering ( CAD / PDK / PCELL / LVS ) 7+ Years

priorities. Experience and Knowledge: Minimum 10+ years of development experience of Mixed Signal CAD design Flows from Front... releases. Development of Calibre Physical Verification decks for cmos PLANAR and FINFET technologies including DRC, LVS, PERC...

Apply Now
Company: Western Digital
Location: Bangalore, Karnataka
Posted Date: 29 Sep 2024

Principal Engineer, ASIC Development Engineering ( CAD / PDK / PCELL / LVS ) 7+Years

priorities. Experience and Knowledge: Minimum 10+ years of development experience of Mixed Signal CAD design Flows from Front... releases. Development of Calibre Physical Verification decks for cmos PLANAR and FINFET technologies including DRC, LVS, PERC...

Apply Now
Company: Western Digital
Location: Bangalore, Karnataka
Posted Date: 29 Sep 2024

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