Job Responsibilities Proficient in Verilog, System Verilog, UVM, object-oriented programming, Firm understanding of constrained random functional verification, coverage, and assertions. Experience with test plan development and developm...
Job Description: Responsibilities: Develop and execute verification plans for complex digital RTL. Utilize the latest verification tools and methodologies, including UVM (Universal Verification Methodology), System Verilog, and formal v...