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Keywords: Memory PHY RTL Design Engineer, Location: Santa Clara, CA

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Memory PHY RTL Design Engineer

_ THE ROLE: The Memory PHY team is looking for a passionate and experienced Design Engineer for RTL and Firmware... design for memory I/O PHY Digital Architecture development from pathfinding, coding, verification to physical implementation...

Posted Date: 31 Mar 2025

Senior E/E & Semiconductor Engineer - Digital Design (RTL) Engineer

Job Role: RTL Engineer Job Location: Santa Clara CA Job description: We are seeking Digital Design (RTL) engineer... for our full time role with Capgemini Engineering. Minimum 10 years of strong experience in Digital design at RTL level using...

Company: Capgemini
Location: Santa Clara, CA
Posted Date: 29 Jan 2025