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Keywords: Lead Engineer - Verification , Location: Bangalore, Karnataka

Page: 4

Advance Lead Engineer

intent & design output. Manage multiple projects simultaneously ensuring project scope & schedule. Prepare Verification.... Experience with design verification processes and hand calculations. Exposure to FEA software (e.g., ANSYS, SolidWorks...

Company: Wabtec
Posted Date: 22 Dec 2024

PD Lead Engineer

clock distribution design and analysis Perform Physical verification activities at full-chip level. Drive technical... Verification, Chip finishing. Should have experience in Physical Design Methodologies and sub-micron technology of 16nm and lower...

Company: Quest Global
Posted Date: 16 Dec 2024

Lead Engineer PD

and above, Expertise in signoff closure – Timing with SI and OCV, Power,IR and Physical Verification at both block and chip level... to GDS Must possess hands on experience in timing closure and physical verification closure Must have handled blocks...

Company: Quest Global
Posted Date: 16 Dec 2024

Senior Lead Engineer - PD

opportunities Perform clock distribution design and analysis Perform Physical verification activities at full-chip level. Drive... Analysis, Physical Verification, Chip finishing. Should have experience in Physical Design Methodologies and sub-micron...

Company: Quest Global
Posted Date: 16 Dec 2024

Lead engineer - DV

, HDL score etc. Working on full chip verification and OVM/UVM Methodology, System Verilog is a must with 3+years of recent... HVL language features or assertions a plus. Should be ARM based SoC verification only. No need to mention tools...

Company: Quest Global
Posted Date: 16 Dec 2024

Lead Engineer-PD

and above, Expertise in signoff closure – Timing with SI and OCV, Power,IR and Physical Verification at both block and chip level... to GDS Must possess hands on experience in timing closure and physical verification closure Must have handled blocks...

Company: Quest Global
Posted Date: 16 Dec 2024

Lead Engineer - Stress

. Should be Good in hand calculations, Verification & interpretation of FE Results Should have good exposure to Fatigue analysis...

Company: Quest Global
Posted Date: 16 Dec 2024

Lead Engineer - DV

verification and OVM/UVM Methodology, System Verilog is a must with 3+years of recent work experience, worked on passing test cases... a plus. Should be ARM based SoC verification only. No need to mention tools. Proficiency in one scripting language like Perl, C++, Python...

Company: Quest Global
Posted Date: 16 Dec 2024

Lead Instrument Engineer

Verification Reports. • Instruments Installation Schedule. Fair knowledge of International Codes & Standards like ISA, IEC, ASME...

Company: Quest Global
Posted Date: 16 Dec 2024

Lead engineer - AMS DV

in existing simulators or stand-alone tools like Surecov, HDL score etc. Working on full chip verification and OVM/UVM... verification only. No need to mention tools. Proficiency in one scripting language like Perl, C++, Python, Unix Make, Unix Shell...

Company: Quest Global
Posted Date: 16 Dec 2024

Lead Engineer - DV

verification and OVM/UVM Methodology, System Verilog is a must with 3+years of recent work experience, worked on passing test cases... a plus. Should be ARM based SoC verification only. No need to mention tools. Proficiency in one scripting language like Perl, C++, Python...

Company: Quest Global
Posted Date: 16 Dec 2024

Lead PD Engineer

verification closure Must have handled blocks of sizes 1M instances and above at frequencies higher than 1GHz Experience...

Company: Quest Global
Posted Date: 16 Dec 2024

Lead Engineer - DV

verification and OVM/UVM Methodology, System Verilog is a must with 3+years of recent work experience, worked on passing test cases... a plus. Should be ARM based SoC verification only. No need to mention tools. Proficiency in one scripting language like Perl, C++, Python...

Company: Quest Global
Posted Date: 16 Dec 2024

Lead Engineer-PD

and above, Expertise in signoff closure – Timing with SI and OCV, Power,IR and Physical Verification at both block and chip level... to GDS Must possess hands on experience in timing closure and physical verification closure Must have handled blocks...

Company: Quest Global
Posted Date: 16 Dec 2024

Lead Engineer PD

and above, Expertise in signoff closure – Timing with SI and OCV, Power,IR and Physical Verification at both block and chip level... to GDS Must possess hands on experience in timing closure and physical verification closure Must have handled blocks...

Company: Quest Global
Posted Date: 16 Dec 2024

Lead Engineer-PD

and above, Expertise in signoff closure – Timing with SI and OCV, Power,IR and Physical Verification at both block and chip level... to GDS Must possess hands on experience in timing closure and physical verification closure Must have handled blocks...

Company: Quest Global
Posted Date: 16 Dec 2024

Lead Engineer

,IR and Physical Verification at both block and chip level, Understanding constraints and fixing techniques, Understanding... level implementation from Netlist to GDS Must possess hands on experience in timing closure and physical verification...

Company: Quest Global
Posted Date: 16 Dec 2024

SMTS Silicon Design Engineer AECG ASIC DV Lead

_ THE ROLE: The focus of this role is to plan, build, and execute the verification of new and existing features for AMD... processor architecture, digital design, and verification in general. You are a team player who has excellent communication...

Posted Date: 24 Oct 2024

Platform Emulation Lead

_ SMTS SYSTEMS DESIGN ENGINEER (Platform Emulation Lead ) THE ROLE: We are looking for a dynamic, energetic Lead... will be necessary towards product development, definition, and root cause resolution. KEY RESPONSIBILITIES: Lead Engineer...

Posted Date: 08 Jan 2025

RTL/Integration- Subsystem/IP Design Lead

_ SMTS SILICON DESIGN ENGINEER THE ROLE: As a member of the Computing and Graphics group, you will help bring to life... Engineer The Person: If you have an experience developing Subsystem by understanding architectural specification, this role...

Posted Date: 05 Jan 2025