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Keywords: DFT Engineer, Location: San Jose, CA

Page: 2

Hardware Test Engineer (Nextest, San Jose, CA)

, and able to succeed within an open collaborative peer environment. As a Hardware Test Engineer you will be responsible... to ensure products are built free of manufacturing defects. Understanding of DFT (Design for Test) and DFM (Design...

Company: Teradyne
Location: San Jose, CA
Posted Date: 17 Nov 2024

Test Timing Engineer

Engineer with strong analytical skills and a deep understanding of timing constraints, such as clock groups, various exceptions... ASIC flow. Background in debugging and analyzing timing constraints, timing closure of DFT modes such as scan shift...

Company: Cisco Systems
Location: San Jose, CA
Posted Date: 08 Nov 2024

Physical Design Engineer

to understand chip architecture and drive DFT requirements early in the design cycle. As a member of this team... you will also be involved in crafting groundbreaking next generation networking chips. You will help lead to drive the DFT and quality process...

Company: Cisco Systems
Location: San Jose, CA
Posted Date: 22 Oct 2024

Staff Digital Design Engineer

Devices, Inc. Job Title: Staff Digital Design Engineer Job Requisition: R243866 Job Location: San Jose, California... of experience as a Design engineer or related role developing digital design for analog mixed signal devices. OR in the...

Company: Analog Devices
Location: San Jose, CA
Posted Date: 18 Oct 2024
Salary: $224250 per year

Digital Design Engineer

. Familiarity with bus protocols (e.g., AXI, AHB) and memory interfaces. Understanding of low-power design techniques and DFT...

Company: Broadcom
Location: San Jose, CA
Posted Date: 19 Dec 2024
Salary: $119000 - 190000 per year

ASIC Principal Engineer

verification, PD, DFT, Package and SW teams to develop next generation AI Switching ASIC Perform diagnostic and post silicon...

Company: Cisco Systems
Location: San Jose, CA
Posted Date: 18 Dec 2024

Lead Test Engineer, ASIC Test Engineering

functional Design and DFT teams to develop and implement test plans Assist with automation of test pattern development...

Company: II-VI
Location: San Jose, CA
Posted Date: 10 Nov 2024

ASIC Design for Test Engineer

and drive DFT requirements early in the design cycle. As a member of this team you will also be involved in crafting... groundbreaking next generation networking chips. You will help lead to drive the DFT and quality process through the entire...

Company: Cisco Systems
Location: San Jose, CA
Posted Date: 01 Nov 2024

ASIC Design Verification Engineer

development expertise in design, DV, DFT, physical design, and post-silicon validation The team comprises micro-architects...

Company: Cisco Systems
Location: San Jose, CA
Posted Date: 29 Oct 2024

ASIC Engineer II (Full Time) United States

development (Standard Cell and I/O), physical design & DFT, Signal Integrity, and complexed packaging technology. Our silicon... design & DFT. Why Cisco #WeAreCisco, where each person is unique, but we bring our talents to work as a team and make...

Company: Cisco Systems
Location: San Jose, CA
Posted Date: 25 Oct 2024
Salary: $108400 - 154200 per year

Design Realization Engineer

- Expertise in Synthesis, Physical Design is desirable - Basic understanding of Clock structures, Power optimization, DFT...

Company: Broadcom
Location: San Jose, CA
Posted Date: 20 Oct 2024
Salary: $91000 - 162000 per year

Physical Design Engineer

, Power optimization, DFT - Deep involvement with multiple chip tapeouts essential - Must have hands-on knowledge...

Company: Broadcom
Location: San Jose, CA
Posted Date: 20 Oct 2024
Salary: $107000 - 190000 per year

Memory Design Engineer

understanding of DFT schemes and chip level integration Familiar with test setups, silicon testing and debug Proficient...

Company: Broadcom
Location: San Jose, CA
Posted Date: 18 Oct 2024
Salary: $119000 - 190000 per year

ASIC Design Technical Leader - Design & Timing Constraints Focus

You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding of timing constraints, including clock...: Being a member of design team who oversees fullchip SDCs and works with physical design and DFT teams to close fullchip...

Company: Cisco Systems
Location: San Jose, CA
Posted Date: 12 Dec 2024

AE Director - Physical Design

. We are excited to welcome highly talented hardware design leaders/managers and application engineer leaders/managers... tools including Synthesis, DFT, and Logical Equivalence Checking Prior experience with Cadence tools such as Genus, Innovus...

Posted Date: 01 Nov 2024

Test Engineering Manager

production resource training needs, define and develop products testing strategies and provide DFT and quoting support. Drive... with 10+ years' experience as a functional test engineer, in industrial, life science, medical device, networking or related...

Company: Sanmina
Location: San Jose, CA
Posted Date: 02 Oct 2024
Salary: $120000 - 145000 per year