Position: Senior Design Verification Engineer Location: Mountainview, CA (Onsite) Experience: 8+ Years Required Skill Sets: Strong expertise along-with complex SoC/IP debug is must At-least 5+ years of experience in System Verilog HV...
Position: Senior Design Verification Engineer Location: Mountainview, CA (Onsite) Experience: 10 Years Responsibilities: Map multi-million gate SoC designs onto prototyping platforms, creating design partitions, FPGA builds, and testbe...