Keywords: Analog Mixed-Signal Modelling Engineer (PHY SerDes Logic Timing), Location: Toronto, ON

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Analog Mixed-Signal Modelling Engineer (PHY + SerDes + Logic Timing)

provides leading-edge SerDes PHY solutions and other Analog Mixed-Signal IPs to support all Marvell products. What You Can... Expect ASIC design engineer responsible the development of behavior models of high-performance SerDes analog circuits...

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Company: Marvell

Location: Toronto, ON

Posted Date: 08 Nov 2024

Analog Mixed-Signal Modelling Engineer

provides leading-edge SerDes PHY solutions and other Analog Mixed-Signal IPs to support all Marvell products. What You Can... with Analog, DSP, Digital Verification, Firmware, and Application Engineering teams to deliver competitive SerDes IP solutions...