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Keywords: ASIC Engineer, Design, Location: Bangalore, Karnataka

Page: 4

Sr. Engineer, Systems Design - C++, STL, Object oriented concepts and data structures

and comfortable with multi core/HW environment Multi-disciplinary experience, including familiarity with Firmware and ASIC design...

Posted Date: 04 Jan 2025

Principal Engineer, Systems Design Engineering

of a global team in multiple geographies Multi-disciplinary experience, including familiarity with Firmware, HW, and ASIC design... and ASIC Registers understanding to interact with FW design. Proficient in C, C++. Experience in SystemC/TLM is preferred...

Posted Date: 04 Jan 2025

Sr. Engineer, Systems Design - C++, STL, Object oriented concepts and data structures

and comfortable with multi core/HW environment Multi-disciplinary experience, including familiarity with Firmware and ASIC design...

Posted Date: 03 Jan 2025

Principal Engineer, Systems Design Engineering

of a global team in multiple geographies Multi-disciplinary experience, including familiarity with Firmware, HW, and ASIC design... and ASIC Registers understanding to interact with FW design. Proficient in C, C++. Experience in SystemC/TLM is preferred...

Posted Date: 03 Jan 2025

RTL design Engineer(Security) - Staff

level design. · Micro architecture and enabling SW teams to use HW blocks. · Running ASIC development tools including... or related work experience. Preferred Qualifications · 5-to 10 years of work experience in ASIC/SoC Design · Experienced...

Company: Qualcomm
Posted Date: 01 Jan 2025

Senior Design Verification Engineer

for block / sub-system level verification. Work with design team in generating test-plans and closure of code and functional... such as design quality, robustness of Design Verification (DV) practice, ease of DV environment integration and make recommendations...

Posted Date: 14 Dec 2024

CPU emulation - Zebu - SDE/MTS/SMTS Silicon Design Engineer

techniques PREFERRED EXPERIENCE: Experience: 3-15 years' experience in processor/ASIC design verification. Experience... teams and plays a critical role in next generation AMD CPU design. Involves having deep understanding of existing AMD X86...

Posted Date: 12 Dec 2024

SD USB Systems Design Engineer

. Job Description The ideal candidate will do the following as part of the System Design Team. * Analyze the Marketing requirements... and conceive product system requirement, in this case SD/uSD of USB products Perform Due Diligence and Design Product features...

Posted Date: 11 Dec 2024

SD USB Systems Design Engineer

. Job Description The ideal candidate will do the following as part of the System Design Team. * Analyze the Marketing requirements... and conceive product system requirement, in this case SD/uSD of USB products Perform Due Diligence and Design Product features...

Posted Date: 11 Dec 2024

SD USB Systems Design Engineer

. Job Description The ideal candidate will do the following as part of the System Design Team. * Analyze the Marketing requirements... and conceive product system requirement, in this case SD/uSD of USB products Perform Due Diligence and Design Product features...

Posted Date: 11 Dec 2024

SD USB Systems Design Engineer

. Job Description The ideal candidate will do the following as part of the System Design Team. * Analyze the Marketing requirements... and conceive product system requirement, in this case SD/uSD of USB products Perform Due Diligence and Design Product features...

Posted Date: 11 Dec 2024

Principal Physical Design Engineer

and execution, Marvell’s custom Processor/ASIC solution offers a differentiated approach with a best-in-class portfolio of data... opportunity to work on both the physical design and methodology for future designs of our next-generation, high-performance...

Company: Marvell
Posted Date: 05 Dec 2024

Digital Design Verification Engineer

Basic Requirement: - Strong digital design fundamentals & basic Electrical engineering - Experience with Verilog.... - Hand on experience in RTL and Gate level simulations of complex ASIC at block and top level - Expert in using simulation...

Posted Date: 01 Dec 2024

Senior Staff Analog Design Engineer

and Storage and ASIC businesses. From industry leading designs of high performance SerDes and PHY, analog front ends to IPs... they meet stringent performance targets. Responsible for design and verification of a complex analog block, work...

Company: Marvell
Posted Date: 29 Nov 2024

RTL Design Engineer - Security/Sr Lead

. Responsible for block level design. · Micro architecture and enabling SW teams to use HW blocks. · Running ASIC development... experience or related work experience. Preferred Qualifications · 10+ years of work experience in ASIC/SoC Design...

Company: Qualcomm
Posted Date: 27 Nov 2024

Staff Design Verification Engineer

for block / sub-system level verification. Work with design team in generating test-plans and closure of code and functional... such as design quality, robustness of Design Verification (DV) practice, ease of DV environment integration and make recommendations...

Posted Date: 24 Nov 2024

Staff Design Verification Engineer

for block / sub-system level verification. Work with design team in generating test-plans and closure of code and functional... such as design quality, robustness of Design Verification (DV) practice, ease of DV environment integration and make recommendations...

Posted Date: 24 Nov 2024

Senior Design Verification Engineer

for block / sub-system level verification. Work with design team in generating test-plans and closure of code and functional... such as design quality, robustness of Design Verification (DV) practice, ease of DV environment integration and make recommendations...

Posted Date: 24 Nov 2024

Senior Digital Design Engineer

& Trace, TZC, SMPU, SPU) and their integration requirements Package Digital IP for seamless integration into design flow... on Power/ Performance/ Area (PPA) and other key qualitative aspects such as design quality, Design For Testability, robustness...

Posted Date: 19 Nov 2024

Digital Design Engineer

more at and on and Job Responsibilities: Design key digital blocks such as accelerators/ datapath IP in Verilog/ System Verilog with built... into design flow at different stages – RTL/ constraints/ CDC waivers, timing wavers, DFT DRCs and waivers, software programming...

Posted Date: 13 Nov 2024